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Syst."],"published-print":{"date-parts":[[2022,7,31]]},"abstract":"<jats:p>High-level synthesis (HLS) is essential to map the high-level language (HLL) description (e.g., in C\/C++) of hardware design to the corresponding Register Transfer Level (RTL) to produce hardware-independent design specifications with reduced design complexity for ASICs and FPGAs. Adopting HLS is crucial for industrial and government applications to lower development costs, verification efforts, and time-to-market. Current research practices focus on optimizing HLS for performance, power, and area constraints. However, the literature does not include an analysis of the security implications carried through HLS-generated RTL translations (e.g., from an untimed high-level sequential specification to a fully scheduled implementation). This article demonstrates the evidence of security vulnerabilities that emerge during the HLS translation of a high-level description of system-on-chip (SoC) intellectual properties to their corresponding RTL. The evidence provided in this manuscript highlights the need for (a) guidelines for high-level programmers to prevent these security issues at the design time and (b) automated HLS verification solutions that cover security in their optimization flow.<\/jats:p>","DOI":"10.1145\/3492345","type":"journal-article","created":{"date-parts":[[2022,1,29]],"date-time":"2022-01-29T13:39:17Z","timestamp":1643463557000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Analyzing Security Vulnerabilities Induced by High-level Synthesis"],"prefix":"10.1145","volume":"18","author":[{"given":"Nitin","family":"Pundir","sequence":"first","affiliation":[{"name":"University of Florida, Gainesville, Florida, USA"}]},{"given":"Sohrab","family":"Aftabjahani","sequence":"additional","affiliation":[{"name":"Intel, San Diego, CA, USA"}]},{"given":"Rosario","family":"Cammarota","sequence":"additional","affiliation":[{"name":"Intel Labs, Hillsboro, OR, USA"}]},{"given":"Mark","family":"Tehranipoor","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, Florida, USA"}]},{"given":"Farimah","family":"Farahmandi","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, Florida, USA"}]}],"member":"320","published-online":{"date-parts":[[2022,1,29]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2188769"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.69"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.5555\/1457713"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593150"},{"key":"e_1_3_2_8_2","unstructured":"J. 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