{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,25]],"date-time":"2025-01-25T19:10:21Z","timestamp":1737832221553,"version":"3.33.0"},"edition-number":"1","reference-count":43,"publisher":"Wiley","isbn-type":[{"type":"print","value":"9780471383932"},{"type":"electronic","value":"9780470050118"}],"license":[{"start":{"date-parts":[[2009,3,16]],"date-time":"2009-03-16T00:00:00Z","timestamp":1237161600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Automatic test generation (ATG) is an essential component in any test strategy. ATG automates the process of finding good tests, which allows the designer to focus on higher level aspects of the test architecture. ATG has a theoretic basis in the Boolean algebra and the logic circuits used to represent and implement, respectively functions in digital systems. Sequential tests complicate the testing process and are handled in one of two ways. First, the sequential machine is unrolled symbolically, which gives it the appearance of a combinational machine. Second, the circuit may be modified to allow for easier and more effective testing. Technology trends continue to present challenges for ATG. These challenges drive an active research community that search for problems associated with the progression of technology that makes testing approaches either more difficult or not effective, intellectual property cores whose internals may not be available to the test designer, and high levels of abstraction used typically in modern design methodologies.<\/jats:p>","DOI":"10.1002\/9780470050118.ecse031","type":"other","created":{"date-parts":[[2008,1,15]],"date-time":"2008-01-15T14:46:25Z","timestamp":1200408385000},"page":"244-262","source":"Crossref","is-referenced-by-count":0,"title":["Automatic Test Generation"],"prefix":"10.1002","author":[{"suffix":"II","given":"Lee A.","family":"Belfore","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2009,3,16]]},"reference":[{"issue":"8","key":"e_1_2_10_2_1","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"Moore G. E.","year":"1965","journal-title":"Electronics"},{"volume-title":"Design and Analysis of Fault\u2010Tolerant Digital Systems","year":"1989","author":"Johnson B. W.","key":"e_1_2_10_3_1"},{"key":"e_1_2_10_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.803640"},{"key":"e_1_2_10_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8578-1"},{"volume-title":"Testing and Reliable Design of CMOS Circuits","year":"1992","author":"Jha N. K.","key":"e_1_2_10_6_1"},{"issue":"6","key":"e_1_2_10_7_1","first-page":"286","article-title":"Physical versus logical fault models in MOS LSI circuits: Impact on their testability","volume":"29","author":"Gailay J.","year":"1980","journal-title":"IEEE Trans. Computers"},{"key":"e_1_2_10_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/41.19071"},{"key":"e_1_2_10_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.55188"},{"volume-title":"Digital Systems Testing and Testable Design","year":"1990","author":"Abramovici M.","key":"e_1_2_10_10_1"},{"volume-title":"Assessing Fault Model and Test Quality","year":"1992","author":"Jha N. K.","key":"e_1_2_10_11_1"},{"key":"e_1_2_10_12_1","doi-asserted-by":"crossref","unstructured":"L. H.GoldsteinandE. L.Thigpen SCOAP: Sandia controllability\/observability analysis program Proceedings of the 17th Conference on Design Automation Minneapolis MN:1980 pp.190\u2013196.","DOI":"10.1145\/800139.804528"},{"key":"e_1_2_10_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.211530"},{"key":"e_1_2_10_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.543707"},{"volume-title":"Fault Detection in Digital Circuits","year":"1971","author":"Friedman A. D.","key":"e_1_2_10_15_1"},{"volume-title":"Switching and Finite Automata Theory","year":"1978","author":"Kohavi Z.","key":"e_1_2_10_16_1"},{"volume-title":"Computers and Intractability: A Guide to the Theory of NP\u2010Completeness","year":"1979","author":"Garey M. R.","key":"e_1_2_10_17_1"},{"key":"e_1_2_10_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.108614"},{"key":"e_1_2_10_19_1","first-page":"277","article-title":"Diagnosis of automata failures: A calculus and a method","volume":"10","author":"Paul Roth J.","year":"1966","journal-title":"IBM J. Res. Devel."},{"key":"e_1_2_10_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224205"},{"issue":"3","key":"e_1_2_10_21_1","first-page":"2l5","article-title":"An implicit enumeration algorithm to generate tests for combinational logic circuits","volume":"30","author":"Goel P.","year":"1981","journal-title":"IEEE Trans. Comp."},{"key":"e_1_2_10_22_1","doi-asserted-by":"crossref","unstructured":"I.HamzaogluandJ. H.Patel Deterministic test pattern generation techniques for sequential circuits DAC 2000 pp.538\u2013543.","DOI":"10.1109\/ICCAD.2000.896528"},{"key":"e_1_2_10_23_1","doi-asserted-by":"crossref","unstructured":"T. M.NiermannandJ. H.Patel HITEC: A test generation package for sequential circuits Proceedings European Design Automation Conference 1990 pp.214\u2013218.","DOI":"10.1109\/EDAC.1991.206393"},{"volume-title":"Genetic Algorithms in Search, Optimization, and Machine Learning","year":"1989","author":"Goldberg D. E.","key":"e_1_2_10_24_1"},{"key":"e_1_2_10_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.700722"},{"key":"e_1_2_10_26_1","doi-asserted-by":"crossref","unstructured":"M. J.Geuzebroek J. Th.van derLinden andA. J.van deGoor Test point insertion that facilitates ATPG in reducing test time and data volume Proceedings of the 2002 International Test Conference (ITC'2002) 2002 pp.138\u2013147.","DOI":"10.1109\/TEST.2002.1041754"},{"key":"e_1_2_10_27_1","unstructured":"H.Vranken F. S.Sapei andH.Wunderlich Impact of test point insertion on silicon area and timing during layout Proceedings of the Design Automatin and test in Europe Conference and Exhibition (DATE'04) 2004."},{"key":"e_1_2_10_28_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.82.0115"},{"key":"e_1_2_10_29_1","unstructured":"E. B.EichelbergerandT. W.Williams A logic design structure for LSI testability Proceedings of the Fourteenth Design Automation Conference New Orleans LA:1977 pp.462\u2013468."},{"key":"e_1_2_10_30_1","unstructured":"S.Funatsu N.Wakatsuki andT.Arima Test generation systems in Japan Proceedings of the Twelfth Design Automation Conference 1975 pp.114\u2013122."},{"key":"e_1_2_10_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223600"},{"issue":"10","key":"e_1_2_10_32_1","doi-asserted-by":"crossref","first-page":"1278","DOI":"10.1109\/43.170990","article-title":"BIST of PCB interconnects using boundary\u2010scan architecture","volume":"41","author":"Hassan A. S. M.","year":"1992","journal-title":"IEEE Trans. Comp."},{"key":"e_1_2_10_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.632881"},{"key":"e_1_2_10_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/96.311775"},{"volume-title":"IEEE Standard Test Access Port and Boundary\u2010Scan Architecture","year":"1990","author":"IEEE","key":"e_1_2_10_35_1"},{"key":"e_1_2_10_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.545970"},{"volume-title":"Built\u2010in Test for VLSI: Pseudorandom Techniques","year":"1987","author":"Bardell P. H.","key":"e_1_2_10_37_1"},{"key":"e_1_2_10_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.52179"},{"key":"e_1_2_10_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.475122"},{"key":"e_1_2_10_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.475124"},{"key":"e_1_2_10_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051391"},{"volume-title":"High\u2010Level Tests Synthesis of Digital VLSI Circuits","year":"1997","author":"Tien\u2010Chien Lee M.","key":"e_1_2_10_42_1"},{"key":"e_1_2_10_43_1","article-title":"Why is ATPG easy","author":"Prasad M. R.","year":"1999","journal-title":"Design Automation Conference"},{"key":"e_1_2_10_44_1","doi-asserted-by":"crossref","unstructured":"R.WeiandA.Sangiovanni\u2010Vincentelli PLATYPUS: A PLA test pattern generation tool 22nd Design Automation Conference 1985 pp.197\u2013203.","DOI":"10.1145\/317825.317856"}],"container-title":["Wiley Encyclopedia of Computer Science and Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/9780470050118.ecse031","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,25]],"date-time":"2025-01-25T18:53:42Z","timestamp":1737831222000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/9780470050118.ecse031"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,3,16]]},"ISBN":["9780471383932","9780470050118"],"references-count":43,"alternative-id":["10.1002\/9780470050118.ecse031","10.1002\/9780470050118"],"URL":"https:\/\/doi.org\/10.1002\/9780470050118.ecse031","archive":["Portico"],"relation":{},"subject":[],"published":{"date-parts":[[2009,3,16]]}}}