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Since the first stateful IMP gate was proposed in 2010, few studies have yet addressed the operating reliability issues that should be resolved before the technology is practically realized. Herein, a feasible near\u2010memory error correction method for a typical bipolar\u2010type memristor stateful logic system is proposed. An error correction principles using a HfO<jats:sub>2<\/jats:sub>\u2010based crossbar array device is explained, and two types of error correction methods checking if the number of FALSE data is zero and if the number of TRUE data is odd are proposed. Although the error correction modules require additional circuits and processing time, the resulting computing efficiency is comparable with conventional stateful logic techniques. Its application with a one\u2010bit full adder is demonstrated and its feasibility for practical stateful logic devices is validated.<\/jats:p><\/jats:sec>","DOI":"10.1002\/aisy.202000081","type":"journal-article","created":{"date-parts":[[2020,6,24]],"date-time":"2020-06-24T03:40:31Z","timestamp":1592970031000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":14,"title":["A Universal Error Correction Method for Memristive Stateful Logic Devices for Practical Near\u2010Memory Computing"],"prefix":"10.1002","volume":"2","author":[{"given":"Jae Hyun","family":"In","sequence":"first","affiliation":[{"name":"Department of Materials Science and Engineering KAIST Advanced Institute of Science and Technology (KAIST)  291 Daehak-ro, Yuseong-gu Daejeon 34141 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Young Seok","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Materials 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