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Simplified analytical device models are prepared from a particular 1S1R device to validate the analysis. The read margin (RM) analysis results show that the <jats:italic>V<\/jats:italic>\/3 voltage scheme and reduced selector leakage are necessary to maximize the RM and maximum operable size <jats:italic>N<\/jats:italic> of the CBA, where <jats:italic>N<\/jats:italic> indicates the number of wires (word line or bit line). The write margin (WM) analysis results show that the unwanted switching of the unselected cell during the write operation is unlikely in the 1S1R CBA even with a large <jats:italic>N<\/jats:italic> value, despite a voltage drop along the interconnection wire. The analysis of simultaneous multiply\u2010and\u2010accumulate operations is conducted using the analytical method to examine the influence of voltage drop according to the wire and memory cells in HNN applications. Reducing the wire resistance and on\u2010state conductance increases the available <jats:italic>N<\/jats:italic> value when the selector operates near the threshold conditions. The proposed analytical model can estimate the maximum accuracy degradation of the HNN through the involvement of the unintentional voltage drop.<\/jats:p><\/jats:sec>","DOI":"10.1002\/aisy.202100174","type":"journal-article","created":{"date-parts":[[2021,11,20]],"date-time":"2021-11-20T04:42:28Z","timestamp":1637383348000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["In\u2010Depth Analysis of One Selector\u2013One Resistor Crossbar Array for Its Writing and Reading Operations for Hardware Neural Network with Finite Wire Resistance"],"prefix":"10.1002","volume":"4","author":[{"given":"Jihun","family":"Kim","sequence":"first","affiliation":[{"name":"Department of Materials Science and Engineering, Seoul National University, and Inter-University Semiconductor Research Center Seoul National University  Gwanak-ro 1, Daehag-dong, Gwanak-gu Seoul 08826 Republic of Korea"}]},{"given":"Hyo Cheon","family":"Woo","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering, Seoul National University, and Inter-University Semiconductor Research Center Seoul National University  Gwanak-ro 1, Daehag-dong, Gwanak-gu Seoul 08826 Republic of Korea"}]},{"given":"Taeyoung","family":"Jeong","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering, Seoul National University, and Inter-University Semiconductor Research Center Seoul National University  Gwanak-ro 1, Daehag-dong, Gwanak-gu Seoul 08826 Republic of Korea"},{"name":"Electronic Materials Center Korea Institute of Science and Technology  5, Hwarang-ro 14-gil, Seongbuk-gu Seoul 02792 Republic of Korea"}]},{"given":"Jung-Hae","family":"Choi","sequence":"additional","affiliation":[{"name":"Electronic Materials Center Korea Institute of Science and Technology  5, Hwarang-ro 14-gil, Seongbuk-gu Seoul 02792 Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6254-9758","authenticated-orcid":false,"given":"Cheol Seong","family":"Hwang","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering, Seoul National University, and Inter-University Semiconductor Research Center Seoul National University  Gwanak-ro 1, Daehag-dong, Gwanak-gu Seoul 08826 Republic of Korea"}]}],"member":"311","published-online":{"date-parts":[[2021,11,20]]},"reference":[{"key":"e_1_2_9_2_1","first-page":"1097","volume":"25","author":"Krizhevsky A.","year":"2012","journal-title":"Adv. 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