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Herein, a method to combine resistance\u2013resistance (<jats:italic>R\u2013R<\/jats:italic>) and voltage\u2013resistance (<jats:italic>V\u2013R<\/jats:italic>) logic gates to implement exclusive logic gates composed of APMR\u2010two\u20102(XOR, IMP, RIMP) and APMR\u2010three\u20104XOR, where APMR means antiparallel memristors with a series resistor, is suggested. The proposed gates can accelerate XOR logic operation in a single cycle and expand for the <jats:italic>n<\/jats:italic>\u2010bit input. The performance of the proposed logic gate is then demonstrated with a 1\u2010bit full adder\u2013subtractor along with the comparison of an <jats:italic>n<\/jats:italic>\u2010bit ripple carry adder. It shows that the implementation for the <jats:italic>n<\/jats:italic>\u2010bit adder takes 4<jats:italic>n<\/jats:italic>+1 memristors within 2<jats:italic>n<\/jats:italic>+1 steps, which significantly improves the optimization in terms of space\u2010 and time\u2010related costs compared with other memristive logic gates. Subsequently, the improved adder circuit can be further utilized to implement an <jats:italic>n<\/jats:italic>\u2010bit multiplier. In addition, the evaluation of the device stress on the various logic gates confirms that the proposed logic gates are reliable.<\/jats:p><\/jats:sec>","DOI":"10.1002\/aisy.202100267","type":"journal-article","created":{"date-parts":[[2022,2,25]],"date-time":"2022-02-25T08:00:25Z","timestamp":1645776025000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Reliable Domain\u2010Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors"],"prefix":"10.1002","volume":"4","author":[{"given":"Taegyun","family":"Park","sequence":"first","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yeong Rok","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jihun","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinwon","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"},{"name":"NAND Function PI SK Hynix Semiconductor, Inc.  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