{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T21:14:13Z","timestamp":1782422053393,"version":"3.54.5"},"reference-count":34,"publisher":"Wiley","issue":"5","license":[{"start":{"date-parts":[[2023,1,20]],"date-time":"2023-01-20T00:00:00Z","timestamp":1674172800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2021R1A3B2079882"],"award-info":[{"award-number":["2021R1A3B2079882"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["advanced.onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Advanced Intelligent Systems"],"published-print":{"date-parts":[[2023,5]]},"abstract":"<jats:sec><jats:label\/><jats:p>In\u2010memory computing using memristor\u2010based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high\u2010energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module\u2010enable signal and input\u2010checker bits.<\/jats:p><\/jats:sec>","DOI":"10.1002\/aisy.202200341","type":"journal-article","created":{"date-parts":[[2023,1,20]],"date-time":"2023-01-20T23:03:48Z","timestamp":1674255828000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Efficient Method for Error Detection and Correction in In\u2010Memory Computing Based on Reliable Ex\u2010Logic Gates"],"prefix":"10.1002","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1138-8747","authenticated-orcid":false,"given":"Taegyun","family":"Park","sequence":"first","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yeong Rok","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dong Hoon","family":"Shin","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Byeol Jun","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6254-9758","authenticated-orcid":false,"given":"Cheol Seong","family":"Hwang","sequence":"additional","affiliation":[{"name":"Department of Materials Science and Engineering and Inter-University Semiconductor Research Center Seoul National University  Seoul 08826 Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"311","published-online":{"date-parts":[[2023,1,20]]},"reference":[{"key":"e_1_2_12_2_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-018-0302-0"},{"key":"e_1_2_12_3_1","doi-asserted-by":"publisher","DOI":"10.1002\/adfm.201600680"},{"key":"e_1_2_12_4_1","doi-asserted-by":"publisher","DOI":"10.1002\/adma.201203680"},{"key":"e_1_2_12_5_1","unstructured":"H. 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