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Specifically, electrical parameter measurements (EPMs) and power\u2010delay product of industrial high\u2010<jats:italic>k<\/jats:italic> metal gate DRAM peripheral 29\u2010stage ring oscillator circuits, including NMOS, PMOS, and interconnects, are focused on. The proposed methods find an optimized input to achieve a lower NN output variance in the gradient descent than one multilayer perceptron (MLP) and mean ensemble of MLPs even when considering the variabilities of the devices and interconnects. The local optima problem of one MLP is resolved by utilizing multiple MLPs trained with different train\/validation data, their trimmed mean, and an additional learnable layer. Moreover, adding the learnable layer secures versatility for various parametric datasets. The methods improve the prediction accuracy (<jats:italic>R<\/jats:italic><jats:sup>2<\/jats:sup>) by 5.6\u201315.6% in sparse data space compared to one MLP and the mean ensemble, decrease the NN output variance of the optimized input by 73.0\u201381.6% compared to one MLP and the mean ensemble, and are successfully verified by implementing it on EPMs of 3977 test patterns of 314 wafers and 16 lots.<\/jats:p>","DOI":"10.1002\/aisy.202300089","type":"journal-article","created":{"date-parts":[[2023,7,8]],"date-time":"2023-07-08T06:30:34Z","timestamp":1688797834000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development"],"prefix":"10.1002","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4597-4389","authenticated-orcid":false,"given":"Hyeok","family":"Yun","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Chang-Hyeon","family":"An","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering Yeungnam University  Gyeongsan 38541 Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0023-5670","authenticated-orcid":false,"given":"Hyundong","family":"Jang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1946-3772","authenticated-orcid":false,"given":"Kyeongrae","family":"Cho","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2530-6033","authenticated-orcid":false,"given":"Jeong-Sik","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering Yeungnam University  Gyeongsan 38541 Republic of Korea"}]},{"given":"Seungjoon","family":"Eom","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Choong-Ki","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of DRAM Development SK hynix Inc.  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