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However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi\u2010device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology\u2010based model parameters using a two\u2010stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current\u2013voltage (<jats:italic>I\u2013V<\/jats:italic>) characteristics of the device. Unlike previous neural compact models, this two\u2010stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade\u2010off. The <jats:italic>I\u2013V<\/jats:italic> characteristics of 1000 amorphous indium\u2013gallium\u2013zinc\u2010oxide thin\u2010film transistor devices with different properties obtained through fully calibrated technology computer\u2010aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average <jats:italic>I<\/jats:italic><jats:sub>DS<\/jats:sub> error of 0.27% and <jats:italic>R<\/jats:italic><jats:sup>2<\/jats:sup> DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.<\/jats:p>","DOI":"10.1002\/aisy.202300435","type":"journal-article","created":{"date-parts":[[2024,1,6]],"date-time":"2024-01-06T07:08:43Z","timestamp":1704524923000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation"],"prefix":"10.1002","volume":"6","author":[{"given":"Seungjoon","family":"Eom","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Hyeok","family":"Yun","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Hyundong","family":"Jang","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Kyeongrae","family":"Cho","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Seunghwan","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"given":"Jinsu","family":"Jeong","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6175-8101","authenticated-orcid":false,"given":"Rock\u2010Hyun","family":"Baek","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering Pohang University of Science and Technology  Pohang 37673 Republic of Korea"}]}],"member":"311","published-online":{"date-parts":[[2024,1,6]]},"reference":[{"key":"e_1_2_8_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM13553.2020.9372010"},{"key":"e_1_2_8_3_1","unstructured":"J.Wang S. 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