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This synaptor has a gate surrounding semiconductor pillar (GSSP) structure with overturned charge injection (OCI) scheme to ensure high capacitive memory window. Sentaurus TCAD simulation tools are used to demonstrate the process feasibility and device characteristics. Two important process parameters are optimized to show the best characteristics; overlap height (<jats:italic>H<\/jats:italic><jats:sub>ov<\/jats:sub>) and channel pillar height (<jats:italic>H<\/jats:italic><jats:sub>ch<\/jats:sub>). An OCI\u2010GSSP device that has an aspect ratio of 10 and the minimal overlap height shows the highest <jats:italic>C<\/jats:italic><jats:sub>on<\/jats:sub>\/<jats:italic>C<\/jats:italic><jats:sub>off<\/jats:sub> over 5 in 40\u2009nm wordline and BL pitch. It is the highest value and the smallest unit device size among the capacitive synapses that have been reported up to now. Advantages of scaled OCI\u2010GSSP devices are appealed through subarray circuit simulation. The subarray composed of OCI\u2010GSSP synaptor can calculate one vector\u2010matrix multiplication operation with energy under 200\u2009fJ and column delay of 3\u2009ns, and result in sufficient signal margin of 275\u2009mV.<\/jats:p>","DOI":"10.1002\/aisy.202400371","type":"journal-article","created":{"date-parts":[[2024,8,22]],"date-time":"2024-08-22T05:49:13Z","timestamp":1724305753000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Capacitive Synaptor with Gate Surrounding Semiconductor Pillar Structure and Overturned Charge Injection for Compute\u2010in\u2010Memory"],"prefix":"10.1002","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0734-6042","authenticated-orcid":false,"given":"Choong\u2010Ki","family":"Kim","sequence":"first","affiliation":[{"name":"DRAM R&amp;D SK Hynix Inc.  2091, Gyeongchung\u2010daero, Bubal\u2010eup Icheon\u2010si Gyeonggi\u2010do 17336 Republic of Korea"},{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology  Atlanta GA 30332 USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Read","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology  Atlanta GA 30332 USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minji","family":"Shon","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology  Atlanta GA 30332 USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tae\u2010Hyeon","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Semiconductor Engineering Seoul National University of Science and Technology  Seoul 01811 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Myung\u2010Su","family":"Kim","sequence":"additional","affiliation":[{"name":"NAND R&amp;D Samsung Electronics  Hwaseong 18448 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ji\u2010Man","family":"Yu","sequence":"additional","affiliation":[{"name":"DRAM R&amp;D SK Hynix Inc.  2091, Gyeongchung\u2010daero, Bubal\u2010eup Icheon\u2010si Gyeonggi\u2010do 17336 Republic of Korea"},{"name":"School of Electrical Engineering Korea Advanced Institute of Science and technology (KAIST)  291 Daehak\u2010ro Daejeon 34141 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Min\u2010Soo","family":"Yoo","sequence":"additional","affiliation":[{"name":"DRAM R&amp;D SK Hynix Inc.  2091, Gyeongchung\u2010daero, Bubal\u2010eup Icheon\u2010si Gyeonggi\u2010do 17336 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang\u2010Kyu","family":"Choi","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering Korea Advanced Institute of Science and technology (KAIST)  291 Daehak\u2010ro Daejeon 34141 Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering Georgia Institute of Technology  Atlanta GA 30332 USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2024,8,22]]},"reference":[{"key":"e_1_2_14_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2021.3092533"},{"key":"e_1_2_14_3_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"e_1_2_14_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.009"},{"key":"e_1_2_14_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MED.2023.3293060"},{"key":"e_1_2_14_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.nanoen.2022.108091"},{"key":"e_1_2_14_7_1","doi-asserted-by":"publisher","DOI":"10.1039\/D0NR03724A"},{"key":"e_1_2_14_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2023.3311344"},{"key":"e_1_2_14_9_1","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.202100258"},{"key":"e_1_2_14_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3243556"},{"key":"e_1_2_14_11_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-021-00649-y"},{"key":"e_1_2_14_12_1","doi-asserted-by":"crossref","unstructured":"S.Mukherjee J.Bizindavyi Y.\u2010C.Luo S.Clima J.Read M. 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