{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T04:30:31Z","timestamp":1773808231643,"version":"3.50.1"},"reference-count":16,"publisher":"Wiley","issue":"10","license":[{"start":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T00:00:00Z","timestamp":1745193600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Bildung und Forschung","doi-asserted-by":"publisher","award":["16ME0995"],"award-info":[{"award-number":["16ME0995"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["advanced.onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Advanced Intelligent Systems"],"published-print":{"date-parts":[[2025,10]]},"abstract":"<jats:p>Neural network (NN)\u2010based compact transistor models have recently emerged as a promising solution to simplify device modeling. However, they are often deployed and evaluated standalone due to the lack of compatibility with existing simulation program with integrated circuit emphasis (SPICE) software. To investigate the benefits of the NN\u2010based compact models, the proposed framework is integrated into commercial SPICE tool, and NN models\u2019 speed is compared with the existing in\u2010built and Verilog\u2010A industry standard implementations. Additionally, the speed\u2010up of NN\u2010based compact models provided by GPU acceleration is demonstrated for variability analysis, and design technology co\u2010optimization with genetic algorithm is explored. For the best trade\u2010off between NN simulation speed and accuracy, the proposed dual\u2010NN structure employs a parameter generator network, representing devices with different transistor geometry, to generate weights for a current\/charge prediction network (CPN). In addition to drain voltage  and gate voltage , CPN also incorporates environment temperature and achieves 0.797%  error with higher than 0.995  scores for DC characteristics. Moreover, it maintains the speed within SPICE, outperforming Verilog\u2010A Berkeley short\u2010channel insulated gate field\u2010effect transistor model (BSIM), and can simulate up to 18.8 million DC points per second with GPU acceleration.<\/jats:p>","DOI":"10.1002\/aisy.202401085","type":"journal-article","created":{"date-parts":[[2025,5,27]],"date-time":"2025-05-27T08:33:22Z","timestamp":1748334802000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Dual Neural Network Framework with SPICE Integration for Fast and Accurate Transistor Modeling"],"prefix":"10.1002","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-6632-9804","authenticated-orcid":false,"given":"Rodion","family":"Novkin","sequence":"first","affiliation":[{"name":"TUM School of Computation, Information and Technology Chair of AI Processor Design Munich Institute of Robotics and Machine Intelligence Technical University of Munich  Munich 85748 Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5649-3102","authenticated-orcid":false,"given":"Hussam","family":"Amrouch","sequence":"additional","affiliation":[{"name":"TUM School of Computation, Information and Technology Chair of AI Processor Design Munich Institute of Robotics and Machine Intelligence Technical University of Munich  Munich 85748 Germany"}]}],"member":"311","published-online":{"date-parts":[[2025,4,21]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2283084"},{"key":"e_1_2_9_3_1","doi-asserted-by":"crossref","unstructured":"J. P.Duarte S.Khandelwal A.Medury C.Hu P.Kushwaha H.Agarwal A.Dasgupta Y. S.Chauhan ESSCIRC Conf. 2015\u2010 41st European Solid\u2010State Circuits Conference (ESSCIRC) Graz Austria September2015 pp.196\u2013201.","DOI":"10.1109\/ESSCIRC.2015.7313862"},{"key":"e_1_2_9_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3208514"},{"key":"e_1_2_9_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3244901"},{"key":"e_1_2_9_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2022.3168243"},{"key":"e_1_2_9_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3251296"},{"key":"e_1_2_9_8_1","doi-asserted-by":"crossref","unstructured":"Z.Zhang R.Wang C.Chen Q.Huang Y.Wang C.Hu D.Wu J.Wang R.Huang 2019 Silicon Nanoelectronics Workshop (SNW) Kyoto Japan June2019 pp.1\u20132.","DOI":"10.23919\/SNW.2019.8782897"},{"key":"e_1_2_9_9_1","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.202300435"},{"key":"e_1_2_9_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3296715"},{"key":"e_1_2_9_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3336305"},{"key":"e_1_2_9_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3048918"},{"key":"e_1_2_9_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2023.3290930"},{"key":"e_1_2_9_14_1","unstructured":"F.Klemme Y.Chauhan J.Henkel H.Amrouch inProc. 39th Int. Conf. on Computer\u2010Aided Design Association for Computing Machinery Virtual Event USA October2020."},{"key":"e_1_2_9_15_1","first-page":"2569","volume":"68","author":"Klemme F.","year":"2021","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"e_1_2_9_16_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"e_1_2_9_17_1","first-page":"8024","volume-title":"Advances in Neural Information Processing Systems 32","author":"Paszke A.","year":"2019"}],"container-title":["Advanced Intelligent Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/advanced.onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/aisy.202401085","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T10:40:51Z","timestamp":1764672051000},"score":1,"resource":{"primary":{"URL":"https:\/\/advanced.onlinelibrary.wiley.com\/doi\/10.1002\/aisy.202401085"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,21]]},"references-count":16,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2025,10]]}},"alternative-id":["10.1002\/aisy.202401085"],"URL":"https:\/\/doi.org\/10.1002\/aisy.202401085","archive":["Portico"],"relation":{},"ISSN":["2640-4567","2640-4567"],"issn-type":[{"value":"2640-4567","type":"print"},{"value":"2640-4567","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,4,21]]},"assertion":[{"value":"2024-12-11","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-04-21","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"2401085"}}