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Through the integration of Muller\u2010C\u2010Element (MCE), Node\u2010Hardened MCE, CLK\u2010Gating MCE (CG\u2010MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. Additionally, it exhibits lower sensitivity to process voltage temperature variations, enabling stable operation in harsh environmental conditions.<\/jats:p>","DOI":"10.1002\/cta.4401","type":"journal-article","created":{"date-parts":[[2024,12,16]],"date-time":"2024-12-16T17:54:25Z","timestamp":1734371665000},"page":"5498-5506","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Novel High\u2010Speed Ultralow Power Double\u2010Node\u2010Upsets Tolerant Automotive Latch Design"],"prefix":"10.1002","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-2565-0608","authenticated-orcid":false,"given":"Guoji","family":"Qiu","sequence":"first","affiliation":[{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences  Shanghai China"},{"name":"University of Chinese Academy of Sciences  Beijing China"}]},{"given":"Dawei","family":"Bi","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences  Shanghai China"}]},{"given":"Zhiyuan","family":"Hu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences  Shanghai China"}]},{"given":"Zhengxuan","family":"Zhang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences  Shanghai China"}]}],"member":"311","published-online":{"date-parts":[[2024,12,16]]},"reference":[{"key":"e_1_2_7_2_1","unstructured":"\u201cAEC\u2010Q100\u2010REV\u2010J \u201d Component Technical Committee Automotive Electronics Council (2023)."},{"key":"e_1_2_7_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2255624"},{"key":"e_1_2_7_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1975.4328188"},{"key":"e_1_2_7_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"e_1_2_7_6_1","unstructured":"\u201cTechnologies|Free Full\u2010Text|SET Pulse Characterization and SER Estimation in Combinational Logic With Placement and Multiple Transient Faults Considerations \u201d Accessed May 11 2024."},{"key":"e_1_2_7_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2260357"},{"key":"e_1_2_7_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2879341"},{"key":"e_1_2_7_9_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0099"},{"key":"e_1_2_7_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2022.04.008"},{"key":"e_1_2_7_11_1","volume-title":"In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","author":"Yamamoto Y.","year":"2018"},{"key":"e_1_2_7_12_1","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E100.C.496"},{"key":"e_1_2_7_13_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics7100247"},{"key":"e_1_2_7_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2849028"},{"key":"e_1_2_7_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2019.2945917"},{"key":"e_1_2_7_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/23.211356"},{"key":"e_1_2_7_17_1","unstructured":"\u201cRadiation Hardened by Design Technique to Mitigate Single Event Transients in Combinational Logic Circuits| IEEE Conference Publication|IEEE Xplore \u201d Accessed: May 10 2024."},{"issue":"3","key":"e_1_2_7_18_1","first-page":"583","article-title":"Basic Mechanisms and Modeling of Single\u2010Event Upset in Digital Microelectronics|","volume":"50","author":"Dodd P. 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