{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:09:48Z","timestamp":1781885388285,"version":"3.54.5"},"reference-count":17,"publisher":"Wiley","issue":"9","license":[{"start":{"date-parts":[[2025,1,2]],"date-time":"2025-01-02T00:00:00Z","timestamp":1735776000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp; Apps"],"published-print":{"date-parts":[[2025,9]]},"abstract":"<jats:title>ABSTRACT<\/jats:title><jats:p>ShiftAddNet is a recently proposed multiplier\u2010less CNN that replaces conventional multiplication with cheaper shift and add operations, which makes it suitable for hardware implementation. In this paper, we present the first implementation of ShiftAddNet FPGA inference core, which achieves low area consumption and fast computation. ShiftAddNet combined the convolutional layer of the DeepShift\u2010PS (denoted as Shift\u2010Accumulate, <jats:italic>sac<\/jats:italic>) and AdderNet (denoted as Add\u2010Accumulate, <jats:italic>aac<\/jats:italic>) into a single computational stage. Due to this reason, there are data dependencies between the <jats:italic>sac<\/jats:italic> and <jats:italic>aac<\/jats:italic>, which prohibits them from being executed in parallel, resulting in \n more operations compared to other multiplier\u2010less CNNs like DeepShift\u2010PS and AdderNet. To overcome this performance bottleneck, we proposed a novel technique to allow pipeline processing between <jats:italic>sac<\/jats:italic> and <jats:italic>aac<\/jats:italic>, effectively reducing the latency. The proposed ShiftAddNet\u201018 was evaluated on a small ResNet\u201018, achieving 11.37\u2009ms of latency per image, which is \n69.21% faster than the original version that takes 19.24\u2009ms. On a denser network, the proposed pipeline ShiftAddNet\u2010101 requires only 61.92\u2009ms as compared to the original version of 98.85\u2009ms, showing a latency reduction of \n37.1%. Compared to the state\u2010of\u2010the\u2010art multiplier\u2010less CNN core (e.g., AdderNet), our work is 20% slower in latency but provides higher accuracy and consumes \n less DSP.<\/jats:p>","DOI":"10.1002\/cta.4419","type":"journal-article","created":{"date-parts":[[2025,1,2]],"date-time":"2025-01-02T23:04:14Z","timestamp":1735859054000},"page":"5538-5547","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Pipeline ShiftAddNet: An FPGA\u2010Based CNN Implementation With Low Hardware Consumption Targeting Constrained Devices"],"prefix":"10.1002","volume":"53","author":[{"given":"Wei\u2010Pau","family":"Kiat","sequence":"first","affiliation":[{"name":"Universiti Tunku Abdul Rahman  Kampar Malaysia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4659-8979","authenticated-orcid":false,"given":"Wai","family":"Kong\u00a0Lee","sequence":"additional","affiliation":[{"name":"Universiti Tunku Abdul Rahman  Kampar Malaysia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hung\u2010Khoon","family":"Tan","sequence":"additional","affiliation":[{"name":"Universiti Tunku Abdul Rahman  Kampar Malaysia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hui\u2010Fuang","family":"Ng","sequence":"additional","affiliation":[{"name":"Universiti Tunku Abdul Rahman  Kampar Malaysia"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"311","published-online":{"date-parts":[[2025,1,2]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11554-020-01044-0"},{"key":"e_1_2_9_3_1","doi-asserted-by":"publisher","DOI":"10.1111\/coin.12594"},{"key":"e_1_2_9_4_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.3957"},{"key":"e_1_2_9_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848647"},{"key":"e_1_2_9_6_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.3834"},{"key":"e_1_2_9_7_1","doi-asserted-by":"publisher","DOI":"10.1049\/ell2.12832"},{"key":"e_1_2_9_8_1","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.8011"},{"key":"e_1_2_9_9_1","unstructured":"Y.Wang M.Huang K.Han et\u00a0al. \u201cAdderNet and Its Minimalist Hardware Design for Energy\u2010Efficient Artificial Intelligence \u201d (2021) arXiv preprint arXiv:2101.10015."},{"key":"e_1_2_9_10_1","doi-asserted-by":"crossref","unstructured":"M.Elhoushi Z.Chen F.Shafiq Y. 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