{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T19:06:53Z","timestamp":1762283213341,"version":"build-2065373602"},"reference-count":26,"publisher":"Wiley","issue":"11","license":[{"start":{"date-parts":[[2025,1,29]],"date-time":"2025-01-29T00:00:00Z","timestamp":1738108800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp; Apps"],"published-print":{"date-parts":[[2025,11]]},"abstract":"<jats:title>ABSTRACT<\/jats:title>\n                  <jats:p>This paper introduces an efficient approach for the rapid detection and rectification of open circuit (OC) and short circuit (SC) switch faults in a single\u2010phase, five\u2010level hybrid multilevel inverter (HMLI). The HMLI system is equipped with both main and redundant units designed to address OC and SC faults. The main unit incorporates an active neutral point clamped (ANPC) leg and a half\u2010bridge leg, whereas the redundant unit consists of an H\u2010bridge. This setup provides multiple switching options for each voltage level, significantly improving fault reconfiguration (FR) capabilities under various fault conditions, including single, double, and triple switch faults, as well as varying utility conditions like changes in modulation index, load, and source. The system employs a data\u2010driven technique for fault detection that uses the inverter's voltage signal as raw data. The discrete Fourier (DF) is applied to convert this voltage signal into a fundamental frequency\u2010based signal, which is then used to determine the threshold for fault detection. Once a fault is detected, the system initiates the FR switching scheme to restore voltage levels, power, and efficiency to their pre\u2010fault state. Additionally, the proposed topology inherently achieves self\u2010voltage balancing in the DC link capacitor and operates with a single DC source configuration. Furthermore, a comprehensive and comparative analysis, including both experimental and simulation studies, is performed to evaluate the effectiveness and robustness of this topology.<\/jats:p>","DOI":"10.1002\/cta.4436","type":"journal-article","created":{"date-parts":[[2025,1,30]],"date-time":"2025-01-30T00:09:31Z","timestamp":1738195771000},"page":"6572-6589","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Automated Fault Detection and Reconfiguration in Five\u2010Level Hybrid Inverter for Enhanced System Resilience"],"prefix":"10.1002","volume":"53","author":[{"given":"Vikram","family":"Singh","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering National Institute of Technology  Raipur Chhattisgarh India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7396-8926","authenticated-orcid":false,"given":"Anamika","family":"Yadav","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering National Institute of Technology  Raipur Chhattisgarh India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shubhrata","family":"Gupta","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering National Institute of Technology  Raipur Chhattisgarh India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2025,1,29]]},"reference":[{"key":"e_1_2_11_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIA.2023.3279359"},{"key":"e_1_2_11_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2018.2890649"},{"key":"e_1_2_11_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/OJIES.2021.3054666"},{"key":"e_1_2_11_5_1","doi-asserted-by":"crossref","unstructured":"K. K.GuptaandS.Jain \u201cA Novel Universal Control Scheme for Multilevel Inverters \u201d in6th IET International Conference on Power Electronics Machines and Drives (PEMD 2012)(Bristol 2012):1\u20136 https:\/\/doi.org\/10.1049\/cp.2012.0176.","DOI":"10.1049\/cp.2012.0176"},{"key":"e_1_2_11_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2023.3242918"},{"key":"e_1_2_11_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/s43236\u2010021\u201000228\u20106"},{"key":"e_1_2_11_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3214320"},{"key":"e_1_2_11_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2017.2750328"},{"key":"e_1_2_11_10_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet\u2010pel.2018.5237"},{"key":"e_1_2_11_11_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet\u2010pel.2019.0672"},{"key":"e_1_2_11_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2024.3402751"},{"key":"e_1_2_11_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2988323"},{"key":"e_1_2_11_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2023.3305000"},{"key":"e_1_2_11_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3126706"},{"key":"e_1_2_11_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPWRD.2023.3244853"},{"key":"e_1_2_11_17_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.prime.2024.100582"},{"key":"e_1_2_11_18_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.egyr.2021.11.058"},{"key":"e_1_2_11_19_1","doi-asserted-by":"crossref","DOI":"10.1016\/j.compeleceng.2021.107481","article-title":"OC Fault Diagnosis of Multilevel Inverter Using SVM Technique and Detection Algorithm","volume":"96","author":"Sarita K.","year":"2021","journal-title":"Computers and Electrical Engineering"},{"key":"e_1_2_11_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2020.3024914"},{"key":"e_1_2_11_21_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet\u2010pel.2018.5176"},{"key":"e_1_2_11_22_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijepes.2021.107185"},{"key":"e_1_2_11_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2021.3102480"},{"key":"e_1_2_11_24_1","doi-asserted-by":"publisher","DOI":"10.1049\/cds2.12033"},{"key":"e_1_2_11_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TTE.2023.3342160"},{"key":"e_1_2_11_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2019.2936271"},{"key":"e_1_2_11_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2016.2624722"}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.4436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T18:59:43Z","timestamp":1762282783000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.4436"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1,29]]},"references-count":26,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2025,11]]}},"alternative-id":["10.1002\/cta.4436"],"URL":"https:\/\/doi.org\/10.1002\/cta.4436","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"type":"print","value":"0098-9886"},{"type":"electronic","value":"1097-007X"}],"subject":[],"published":{"date-parts":[[2025,1,29]]},"assertion":[{"value":"2024-08-27","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-01-05","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-01-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}