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Additionally, the drain\u2010source voltage of the MOS transistor is utilized to generate a dead\u2010zone voltage, which reduces the impact on the secondary pole frequency and further improves stability. A non\u2010binary weighted capacitor array is employed in the two\u2010stage sub\u2010ADC to provide redundancy, reduce settling time, improve speed, and work in conjunction with the common\u2010mode stable switching timing. This approach solves the problem that traditional switching timing can only correct one\u2010sided settling errors, thereby fully exploiting the redundancy's correction capability. The prototype ADC was fabricated in a 65\u2010nm CMOS process and consumes 5.85\u2009mW from a 1.1\u2010V power supply at 80 MS\/s. The SNDR and SFDR are 53.93 and 70.33\u2009dB, respectively, with a Nyquist input, achieving a Walden figure\u2010of\u2010merit (FoM) of 179 fJ\/conversion\u2010step.<\/jats:p>","DOI":"10.1002\/cta.4442","type":"journal-article","created":{"date-parts":[[2025,2,7]],"date-time":"2025-02-07T02:26:07Z","timestamp":1738895167000},"page":"5862-5874","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An 80\u2010MS\/s 60.9\u2010dB SNDR Fully Differential Ring Amplifier\u2010Based SAR\u2010Assisted Pipelined ADC With Dual Redundancy in 65\u2010nm CMOS"],"prefix":"10.1002","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-9878-3377","authenticated-orcid":false,"given":"Hao","family":"Chen","sequence":"first","affiliation":[{"name":"School of Information Engineering Guangdong University of Technology  Guangzhou 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