{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,15]],"date-time":"2025-11-15T04:07:07Z","timestamp":1763179627368,"version":"build-2065373602"},"reference-count":25,"publisher":"Wiley","issue":"10","license":[{"start":{"date-parts":[[2025,2,4]],"date-time":"2025-02-04T00:00:00Z","timestamp":1738627200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp;amp; Apps"],"published-print":{"date-parts":[[2025,10]]},"abstract":"<jats:title>ABSTRACT<\/jats:title><jats:p>In this paper, a stress\u2010relaxed driver system applied to compute\u2010in\u2010memory (CIM) is proposed for programming, reading and erasing of the CIM chip. The driver system utilizes a hierarchical regulation method to achieve accurate row and column selectivity, reducing the area overhead of the peripheral driver system for the CIM array. In order to suppress the voltage fluctuation of the power supply and ground caused by direct path currents, power\u2010delay efficient positive and negative voltage level shifters are proposed. The proposed level shifters allows transistors used in the driver system to switch voltages at the safe operating limit. The driver system based on 1024 \n 2048 floating gate devices is implemented using a 65\u2010nm CMOS process. The driver system converts a 1.8\u2010V voltage\u2010domain input signal to a high\u2010voltage\u2010domain output voltage, which meets the requirements of operating transmissions from \u221210 to 9 V. The simulation results show that the maximum voltage stress in the driver system is less than 12 V, achieving a reduction of 21.9% compared to the previous study. Simultaneous switching of 256 word\u2010lines can be achieved across the temperature range of \u221240\u00b0C to 125\u00b0C with a 2\u2010pF capacitive load. The driver system can support the switching of the program, erase, and read modes. In the read mode, the delay remains less than 13 ns for the gate voltage of floating gate devices ranging from 3 to 7 V. We conducted the comparative analysis and simulations of the proposed level shifters to elucidate pertinent design trade\u2010offs. The comparison results show that the proposed level shifters exhibit significant advantages in peak current and power consumption compared with the topologies of various level shifters and have the lowest power\u2010delay product.<\/jats:p>","DOI":"10.1002\/cta.4463","type":"journal-article","created":{"date-parts":[[2025,2,4]],"date-time":"2025-02-04T23:35:39Z","timestamp":1738712139000},"page":"5715-5728","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Stress\u2010Relaxed Driver System Using Power\u2010Delay Efficient Level Shifters for Compute\u2010in\u2010Memory Based on the Floating Gate Devices"],"prefix":"10.1002","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3435-8628","authenticated-orcid":false,"given":"Zhiguo","family":"Yu","sequence":"first","affiliation":[{"name":"School of Integrated Circuits Jiangnan University  Wuxi China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-9129-0100","authenticated-orcid":false,"given":"Yating","family":"Dong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Jiangnan University  Wuxi China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yang","family":"Qiao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Jiangnan University  Wuxi China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhengyuan","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Jiangnan University  Wuxi China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xuyuan","family":"Gu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Jiangnan University  Wuxi China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaofeng","family":"Gu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Jiangnan University  Wuxi China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2025,2,4]]},"reference":[{"key":"e_1_2_10_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2021.3114407"},{"key":"e_1_2_10_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3004543"},{"key":"e_1_2_10_4_1","doi-asserted-by":"crossref","unstructured":"W.Kang H.Zhang andW.Zhao \u201cSpintronic Memories: From Memory to Computing\u2010in\u2010Memory \u201d in2019 IEEE\/ACM International Symposium on Nanoscale Architectures (NANOARCH) Qingdao China. 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