{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,18]],"date-time":"2025-05-18T05:22:15Z","timestamp":1747545735038,"version":"3.33.0"},"reference-count":16,"publisher":"Wiley","issue":"6","license":[{"start":{"date-parts":[[2006,12,19]],"date-time":"2006-12-19T00:00:00Z","timestamp":1166486400000},"content-version":"vor","delay-in-days":5527,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Circuit Theory &amp; Apps"],"published-print":{"date-parts":[[1991,11]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Even where a satisfactory circuit design has been achieved, it is often the case that, owing to variations in the manufacturing process, some of the samples of a mass\u2010produced circuit will violate the specifications on performance so that the manufacturing yield is less than 100%. Such an undesirable effect can, however, be minimized or even eliminated by redesign of the circuit to the extent of changing parameter values while retaining the original circuit topology. For discrete component circuits algorithms are available to achieve such redesign. the special characteristics of integrated circuits, however, are such that these methods are unsuitable as they stand. Two new algorithms for handling the yield enhancement of integrated circuits are described and their successful application is illustrated in the context of two\u2010stage CMOS op amps.<\/jats:p>","DOI":"10.1002\/cta.4490190605","type":"journal-article","created":{"date-parts":[[2007,7,2]],"date-time":"2007-07-02T01:46:35Z","timestamp":1183340795000},"page":"565-578","source":"Crossref","is-referenced-by-count":14,"title":["The Parametric Yield Enhancement of Integrated Circuits"],"prefix":"10.1002","volume":"19","author":[{"given":"Miran","family":"Singha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Spence","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2006,12,19]]},"reference":[{"volume-title":"Tolerance Design of Electronic Circuits","year":"1988","author":"Spence R.","key":"e_1_2_1_2_2"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1977.1084353"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1982.1085115"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1981.1085029"},{"key":"e_1_2_1_6_2","first-page":"816","volume-title":"IEEE Int. Symp. on Circuits and Systems","author":"Wehrhahn E.","year":"1988"},{"key":"e_1_2_1_7_2","first-page":"260","article-title":"Statistical exploration approach to design centering","volume":"127","author":"Soin R. S.","year":"1980","journal-title":"Proc. IEE"},{"key":"e_1_2_1_8_2","first-page":"1424","volume-title":"Proc. IEEE 1984 Int. Symp. on Circuits and Systems","author":"Wehrhahn E.","year":"1985"},{"key":"e_1_2_1_9_2","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1109\/TCAD.1984.1270055","article-title":"Fabrics\u2010II: a statistically based IC fabrication process simulator","volume":"3","author":"Nassif S. R.","year":"1984","journal-title":"IEEE Trans. Computer\u2010aided Design"},{"key":"e_1_2_1_10_2","first-page":"194","volume-title":"A new methodology for the design centering of IC fabrication processes","author":"Low K. K.","year":"1990"},{"key":"e_1_2_1_11_2","unstructured":"M.SinghaandR.Spence Tolerance design of analogue integrated circuits' ASCOT Project Report Imperial College December1989."},{"key":"e_1_2_1_12_2","unstructured":"M.Singha X\u2010M.XiaoandR.Spence The automated improvement of analogue integrated circuits' IEE Colloq. Digest 1990\/107 June1990."},{"key":"e_1_2_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270172"},{"key":"e_1_2_1_14_2","doi-asserted-by":"crossref","unstructured":"T.MukherjeeandL. R.Carley Rapid yield estimation as a computer aid for analog cell design' IEEE 1990 Custom Integrated Circuits Conf. IEEE New York 1991 pp.8.5.1\u20138.5.4.","DOI":"10.1109\/CICC.1990.124690"},{"key":"e_1_2_1_15_2","first-page":"190","volume-title":"IEEE 1989 Int. Conf. on Computer\u2010aided Design","author":"Yu T. K.","year":"1990"},{"key":"e_1_2_1_16_2","first-page":"116","volume-title":"IEEE 1990 Int. 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Digest 1990\/073 May1990."}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fcta.4490190605","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.4490190605","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T02:08:01Z","timestamp":1737166081000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.4490190605"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1991,11]]},"references-count":16,"journal-issue":{"issue":"6","published-print":{"date-parts":[[1991,11]]}},"alternative-id":["10.1002\/cta.4490190605"],"URL":"https:\/\/doi.org\/10.1002\/cta.4490190605","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"type":"print","value":"0098-9886"},{"type":"electronic","value":"1097-007X"}],"subject":[],"published":{"date-parts":[[1991,11]]}}}