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The LODSL latch uses polarity design and source isolation technology to reduce the number of sensitive nodes. The latch does not adopt the redundant design, reduces the circuit overhead and area, adopts D to Q transmission pathway and clock gating technology, and has the characteristics of low power consumption and low delay. Simulation results indicate that, in comparison to the recent DNU self\u2010recoverable latch design, the LODSL latch has achieved an average reduction of 50.8% in power consumption, 40.3% in delay, 35.6% in area, and 79.4% in power\u2010delay\u2010area product (PDAP), and it still has good robustness under different PVT conditions.<\/jats:p>","DOI":"10.1002\/cta.4523","type":"journal-article","created":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T14:54:35Z","timestamp":1743346475000},"page":"6665-6674","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Low Overhead Double\u2010Node\u2010Upset Self\u2010Recoverable Latch Based on Polarity Design and Source Isolation Technology"],"prefix":"10.1002","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0278-5804","authenticated-orcid":false,"given":"Qiang","family":"Zhao","sequence":"first","affiliation":[{"name":"School of Integrated Circuits Anhui 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