{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,9]],"date-time":"2026-03-09T00:16:05Z","timestamp":1773015365272,"version":"3.50.1"},"reference-count":29,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2025,5,19]],"date-time":"2025-05-19T00:00:00Z","timestamp":1747612800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"},{"start":{"date-parts":[[2025,5,19]],"date-time":"2025-05-19T00:00:00Z","timestamp":1747612800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp; Apps"],"published-print":{"date-parts":[[2026,2]]},"abstract":"<jats:title>ABSTRACT<\/jats:title>\n                  <jats:p>DC\u2010DC converters based on partial power processing (PPP) offer the advantage of high power density and high efficiency and are considered an attractive solution in various systems like photovoltaic systems, energy storage systems. It has been demonstrated that PPP topologies can be synthesized starting from buck\u2010boost converter in a limited number of steps. Based on these steps, this paper proposes a new rapid modeling method for PPP topologies. It has been demonstrated that the voltage gains of all synthesized topologies can be obtained from the voltage gain of buck\u2010boost converter and the corresponding voltage gain formulas. Similarly, the models of all synthesized topologies can be obtained from the model of buck\u2010boost converter and the corresponding modeling formulas. This method requires no manual circuit analysis, only a computer to execute the program. It is rapid and significantly simplifies the modeling process. The proposed modeling method is validated through the models of several classic topologies and frequency sweeping in the simulation.<\/jats:p>","DOI":"10.1002\/cta.4589","type":"journal-article","created":{"date-parts":[[2025,5,19]],"date-time":"2025-05-19T09:36:11Z","timestamp":1747647371000},"page":"782-794","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Rapid Modeling Method of Partial Power Processing Architecture With Circuit\u2010Analysis\u2010Free Based on State\u2010Space Averaging"],"prefix":"10.1002","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5432-9325","authenticated-orcid":false,"given":"Ye","family":"Tian","sequence":"first","affiliation":[{"name":"School of Electrical Engineering Beijing Jiaotong University  Beijing China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yan","family":"Li","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering Beijing Jiaotong University  Beijing China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fangyi","family":"Wei","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering Beijing Jiaotong University  Beijing China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2025,5,19]]},"reference":[{"key":"e_1_2_8_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2999062"},{"key":"e_1_2_8_3_1","doi-asserted-by":"crossref","unstructured":"R. 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D.","year":"2008","journal-title":"IEEE Transactions on Industrial Electronics"},{"key":"e_1_2_8_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2016.2533347"},{"key":"e_1_2_8_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIA.2019.2921295"},{"key":"e_1_2_8_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2019.2945264"},{"key":"e_1_2_8_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2019.2915248"},{"key":"e_1_2_8_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2021.3082869"},{"key":"e_1_2_8_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.1966.1065901"},{"key":"e_1_2_8_13_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.815"},{"key":"e_1_2_8_14_1","doi-asserted-by":"crossref","unstructured":"J. R. R.Zientarski J. R.Pinheiro M. L.daSilva Martins andH. L.Hey \u201cUnderstanding the Partial Power Processing Concept: A Case\u2010Study of Buck\u2010Boost DC\/DC Series Regulator \u201d in2015 IEEE 13th Brazilian Power Electronics Conference and 1st Southern Power Electronics Conference (COBEP\/SPEC)(IEEE 2015) 1\u20136.","DOI":"10.1109\/COBEP.2015.7420092"},{"key":"e_1_2_8_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2017.2765928"},{"key":"e_1_2_8_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2018.2869370"},{"key":"e_1_2_8_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2021.3138299"},{"key":"e_1_2_8_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2021.3102180"},{"key":"e_1_2_8_19_1","doi-asserted-by":"publisher","DOI":"10.6113\/JPE.2013.13.3.349"},{"key":"e_1_2_8_20_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-43881-4_14"},{"key":"e_1_2_8_21_1","doi-asserted-by":"crossref","unstructured":"C.Li Y. E.Bouvier A.Berrios P.Alou J. A.Oliver andJ. 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