{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,9]],"date-time":"2026-03-09T00:16:00Z","timestamp":1773015360855,"version":"3.50.1"},"reference-count":26,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T00:00:00Z","timestamp":1748476800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"},{"start":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T00:00:00Z","timestamp":1748476800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp; Apps"],"published-print":{"date-parts":[[2026,2]]},"abstract":"<jats:title>ABSTRACT<\/jats:title>\n                  <jats:p>Common\u2010ground switched\u2010capacitor (CGSC) inverters show unique advantages in voltage boosting and eliminating leakage current due to the combination of switched\u2010capacitor and common\u2010ground structure. However, the existing CGSC inverters have a drawback in that the unbalanced AC output voltage waveform will lead to DC bias. To address this problem, a CGSC five\u2010level inverter with low\u2013DC bias characteristics is proposed in this article. The topology consists of a single\u2013DC input voltage, 11 switches, two diodes, and three capacitors. The inherent circuit feature enables the hybrid modulation strategy to repeatedly charge the capacitors using the DC source, optimizing the voltage ripples. By further designing the capacitance to compensate for the asymmetry of the voltage ripple, the output DC bias can be effectively suppressed. This article details how the topology works and the hybrid modulation strategies, as well as capacitance analysis. In addition, a performance comparison analysis with other similar topologies highlights the advantages of the proposed topology to suppress DC bias and improve capacitor utilization. The simulation results show the suppression effect with the hybrid modulation strategy and ripple compensation. Finally, a 500\u2010W experimental prototype was built to verify the feasibility of the proposed topology.<\/jats:p>","DOI":"10.1002\/cta.70000","type":"journal-article","created":{"date-parts":[[2025,5,29]],"date-time":"2025-05-29T03:35:05Z","timestamp":1748489705000},"page":"742-756","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A Common\u2010Ground Structure Switched\u2010Capacitor Multilevel Inverter With Low\u2013DC Bias Characteristics"],"prefix":"10.1002","volume":"54","author":[{"given":"Kejiang","family":"Liu","sequence":"first","affiliation":[{"name":"College of Automation Guangdong Polytechnic Normal University  Guangzhou China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-1737-9358","authenticated-orcid":false,"given":"Zejia","family":"Lin","sequence":"additional","affiliation":[{"name":"College of Automation Guangdong Polytechnic Normal University  Guangzhou China"}]},{"given":"Xianyong","family":"Zhang","sequence":"additional","affiliation":[{"name":"College of Automation Guangdong Polytechnic Normal University  Guangzhou China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0090-2269","authenticated-orcid":false,"given":"Shili","family":"Lin","sequence":"additional","affiliation":[{"name":"College of Automation Guangdong Polytechnic Normal University  Guangzhou China"}]},{"given":"Li","family":"Li","sequence":"additional","affiliation":[{"name":"College of Automation Guangdong Polytechnic Normal University  Guangzhou China"}]}],"member":"311","published-online":{"date-parts":[[2025,5,29]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2015.2406315"},{"key":"e_1_2_9_3_1","doi-asserted-by":"publisher","DOI":"10.3390\/en16155638"},{"key":"e_1_2_9_4_1","doi-asserted-by":"publisher","DOI":"10.3390\/en16134972"},{"key":"e_1_2_9_5_1","doi-asserted-by":"crossref","unstructured":"A.Shawky T.Takeshita andM. A.Sayed \u201cAnalysis and Performance Evaluation of Single\u2010Stage Three\u2010Phase SEPIC Differential Inverter With Continuous Input Current for PV Grid\u2010Connected Applications \u201d in2021 IEEE Applied Power Electronics Conference and Exposition (APEC) (IEEE 2021):2719\u20132726.","DOI":"10.1109\/APEC42165.2021.9487141"},{"key":"e_1_2_9_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2020.3029480"},{"key":"e_1_2_9_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2014.2350978"},{"key":"e_1_2_9_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2017.2772323"},{"key":"e_1_2_9_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2020.2973340"},{"key":"e_1_2_9_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2023.3299027"},{"key":"e_1_2_9_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2022.3197393"},{"key":"e_1_2_9_12_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.4375"},{"key":"e_1_2_9_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2021.3066932"},{"key":"e_1_2_9_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2021.3075874"},{"key":"e_1_2_9_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/jestpe.2019.2891937"},{"key":"e_1_2_9_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2016.2623568"},{"key":"e_1_2_9_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTPE.2020.2979158"},{"key":"e_1_2_9_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2020.3028810"},{"key":"e_1_2_9_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/JESTIE.2023.3281252"},{"key":"e_1_2_9_20_1","doi-asserted-by":"publisher","DOI":"10.3390\/en16114269"},{"key":"e_1_2_9_21_1","doi-asserted-by":"publisher","DOI":"10.3390\/en14227643"},{"key":"e_1_2_9_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2020.3035598"},{"key":"e_1_2_9_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2983654"},{"key":"e_1_2_9_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2023.3314896"},{"key":"e_1_2_9_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2020.2967336"},{"key":"e_1_2_9_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.2019.2940539"},{"key":"e_1_2_9_27_1","doi-asserted-by":"publisher","DOI":"10.1049\/pel2.12110"}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.70000","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/full-xml\/10.1002\/cta.70000","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.70000","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,8]],"date-time":"2026-03-08T23:13:32Z","timestamp":1773011612000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.70000"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5,29]]},"references-count":26,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2026,2]]}},"alternative-id":["10.1002\/cta.70000"],"URL":"https:\/\/doi.org\/10.1002\/cta.70000","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"value":"0098-9886","type":"print"},{"value":"1097-007X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,5,29]]},"assertion":[{"value":"2025-01-04","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-05-20","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-05-29","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}