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When the bang\u2010bang\u2010based digital PLL (BB\u2010DPLL) cannot fully track the DCO jitter, the jitter slewing effect exacerbates the in\u2010band noise. The proposed DSBPLL can increase the PLL filter order without using a high\u2010order loop filter, thereby mitigating the in\u2010band noise caused by input tracking jitter. Theoretical noise analysis confirmed that the proposed DSBPLL can reduce 54.3% of the integrated jitter from 100\u2009kHz to 100\u2009MHz, consistent with the measurement results.<\/jats:p>","DOI":"10.1002\/cta.70013","type":"journal-article","created":{"date-parts":[[2025,6,7]],"date-time":"2025-06-07T07:45:21Z","timestamp":1749282321000},"page":"507-516","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Design and Analysis of \u0394\u03a3 Modulator Analogous Bang\u2010Bang Digital PLL"],"prefix":"10.1002","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-6994-5026","authenticated-orcid":false,"given":"Minsu","family":"Park","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Computer Science Daegu Gyeongbuk Institute of Science and Technology (DGIST)  Daegu South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7373-7028","authenticated-orcid":false,"given":"Jong\u2010Hyeok","family":"Yoon","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science Daegu Gyeongbuk Institute of Science and Technology (DGIST)  Daegu South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8036-3965","authenticated-orcid":false,"given":"Minyoung","family":"Song","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science Daegu Gyeongbuk Institute of Science and Technology (DGIST)  Daegu South Korea"}]}],"member":"311","published-online":{"date-parts":[[2025,6,7]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.885649"},{"key":"e_1_2_9_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2414924"},{"key":"e_1_2_9_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2017.2689738"},{"key":"e_1_2_9_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3019344"},{"key":"e_1_2_9_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2022.3147954"},{"key":"e_1_2_9_7_1","doi-asserted-by":"crossref","unstructured":"P.Meinerzhagen C.Tokunaga A.Malavasiet\u00a0al.2018. \u201cAn Energy\u2010Efficient Graphics Processor Featuring Fine\u2010Grain DVFS With Integrated Voltage Regulators Execution\u2010Unit Turbo and Retentive Sleep in 14nm Tri\u2010Gate CMOS\u201d. in Proc. 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