{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,8]],"date-time":"2026-03-08T23:15:59Z","timestamp":1773011759758,"version":"3.50.1"},"reference-count":27,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T00:00:00Z","timestamp":1751587200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"},{"start":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T00:00:00Z","timestamp":1751587200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/doi.wiley.com\/10.1002\/tdm_license_1.1"}],"funder":[{"DOI":"10.13039\/501100003995","name":"Natural Science Foundation of Anhui Province","doi-asserted-by":"publisher","award":["2308085MF207"],"award-info":[{"award-number":["2308085MF207"]}],"id":[{"id":"10.13039\/501100003995","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory &amp;amp; Apps"],"published-print":{"date-parts":[[2026,3]]},"abstract":"<jats:title>ABSTRACT<\/jats:title>\n                  <jats:p>This article presents a successive approximation register (SAR) ADC that incorporates an intermediate\u2010voltage dynamic comparator and calibration scheme for quantitative decoupling. The background calibration process of an ADC often occupies the time allocated for quantization, thereby limiting the operational speed of the ADC. To mitigate this issue, a novel calibration timing scheme has been proposed that can effectively decouple the calibration process from the quantization phase by integrating two additional switches at the input of the comparator. Furthermore, to overcome the constraint imposed by the comparator on the quantization speed and precision of SAR ADCs, an intermediate\u2010voltage dynamic comparator architecture has been developed. Compared with traditional double tail dynamic comparator, this innovative design enhances performance by leveraging intermediate values to trigger comparison results, thereby achieving faster and more efficient comparison outcomes. The designed ADC is simulated using a 65\u2010nm CMOS technology and operates at a power supply voltage of 1.2\u2009V. Post\u2010simulation results reveal that the ADC achieves a signal\u2010to\u2010noise and distortion ratio (SNDR) of 59.34 dB at a sampling frequency of 120 MHz. Additionally, the power consumption is measured at 1.18 mW, and the figure of merit (FOM\n) is calculated to be 13.03 fJ\/conv\u2010step.<\/jats:p>","DOI":"10.1002\/cta.70055","type":"journal-article","created":{"date-parts":[[2025,7,5]],"date-time":"2025-07-05T01:44:08Z","timestamp":1751679848000},"page":"1268-1280","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A 10\u2010Bit 120\u2010MS\/s SAR ADC With Intermediate\u2010Voltage Dynamic Comparator and Calibration Scheme for Quantitative Decoupling"],"prefix":"10.1002","volume":"54","author":[{"given":"Xuanhe","family":"Zhang","sequence":"first","affiliation":[{"name":"School of Microelectronics Hefei University of Technology  Hefei China"}]},{"given":"Huijuan","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics Hefei University of Technology  Hefei China"}]},{"given":"Yuchen","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Microelectronics Hefei University of Technology  Hefei China"}]},{"given":"Aoyun","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Microelectronics Hefei University of Technology  Hefei China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3510-4585","authenticated-orcid":false,"given":"Zhang","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Microelectronics Hefei University of Technology  Hefei China"}]}],"member":"311","published-online":{"date-parts":[[2025,7,4]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048139"},{"key":"e_1_2_9_3_1","doi-asserted-by":"crossref","unstructured":"S.\u2010W. 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Digest of Technical Papers (2007):314\u2013605.","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"e_1_2_9_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2241799"},{"key":"e_1_2_9_20_1","doi-asserted-by":"crossref","unstructured":"A.Agnes E.Bonizzoni P.Malcovati andF.Maloberti \u201cA 9.4\u2010ENOB 1V 3.8\u03bcW 100kS\/s SAR ADC With Time\u2010Domain Comparator \u201d in2008 IEEE International Solid\u2010State Circuits Conference \u2010 Digest of Technical Papers (2008):246\u2013610.","DOI":"10.1109\/ISSCC.2008.4523149"},{"key":"e_1_2_9_21_1","doi-asserted-by":"crossref","unstructured":"L.Zhang D.Li Z.Zhu andY.Yang \u201cAn 8\u2010Bit 500\u2010MS\/s Asynchronous Single\u2010Channel SAR ADC in 65 nm CMOS \u201d (2015) Analog Integrated Circuits and Signal Processing.","DOI":"10.1007\/s10470-015-0512-4"},{"key":"e_1_2_9_22_1","doi-asserted-by":"crossref","unstructured":"X.Tang Y.Shen X.Xin et\u00a0al. \u201cA 10\u2010Bit 100\u2010MS\/s SAR ADC With Always\u2010On Reference Ripple Cancellation \u201d in2020 IEEE Symposium on VLSI Circuits (2020):1\u20132.","DOI":"10.1109\/VLSICircuits18222.2020.9162786"},{"issue":"11","key":"e_1_2_9_23_1","first-page":"2307","article-title":"An 8\u2010Bit 2.1\u2010mW 350\u2010MS\/s SAR ADC With 1.5 b\/Cycle Redundancy in 65\u2010nm CMOS","volume":"67","author":"Li D.","year":"2020","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_2_9_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3184010"},{"key":"e_1_2_9_25_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2793"},{"key":"e_1_2_9_26_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.3577"},{"key":"e_1_2_9_27_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2022.154256"},{"key":"e_1_2_9_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2024.106435"}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.70055","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/full-xml\/10.1002\/cta.70055","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.70055","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,8]],"date-time":"2026-03-08T21:44:37Z","timestamp":1773006277000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.70055"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,4]]},"references-count":27,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2026,3]]}},"alternative-id":["10.1002\/cta.70055"],"URL":"https:\/\/doi.org\/10.1002\/cta.70055","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"value":"0098-9886","type":"print"},{"value":"1097-007X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,7,4]]},"assertion":[{"value":"2025-03-04","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-06-23","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2025-07-04","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}