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The key expansions with respect to AES 128\u2010bit, AES 192\u2010bit, and AES 256\u2010bit are fused into a single module to reduce the circuit area overhead. By optimizing the AES encryption\/decryption circuit with a 14\u2010stage pipeline, the whole cryptographic engine is able to make the three previous AES key lengths compatible. Furthermore, in order to resist against differential power analysis (DPA) attacks, two DPA attack countermeasures are embedded into the AES engine to randomize the critical power leakage. One countermeasure is randomly altering the number of pipelined stages with 14 or 16. The other countermeasure randomizes the mathematical operation pertaining to substitution boxes (S\u2010boxes). The results show that the proposed DPA\u2010resistant and reconfigurable (DRR) AES engine is capable of achieving a 128 Gbps throughput and with 98,131 \nm\n area, under the synthesis of TSMC 16\u2010nm process design kits (PDK). Additionally, even if 10 million plaintexts are enabled, the secret key of the DRR AES engine cannot be revealed by DPA attacks.<\/jats:p>","DOI":"10.1002\/cta.70073","type":"journal-article","created":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T09:01:08Z","timestamp":1753174868000},"page":"1385-1399","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A DPA\u2010Resistant and Reconfigurable AES Cryptographic Engine Design and Implementation"],"prefix":"10.1002","volume":"54","author":[{"given":"Zhaoyi","family":"Niu","sequence":"first","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan China"}]},{"given":"Zhaokang","family":"Peng","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan China"}]},{"given":"Nengyuan","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan 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Integrated Circuits Shandong University  Jinan China"}]},{"given":"Jiawei","family":"Zhang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan China"}]},{"given":"Linhan","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan China"}]},{"given":"Kangning","family":"Song","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8720-3083","authenticated-orcid":false,"given":"Weize","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits Shandong University  Jinan China"},{"name":"Quan Cheng Laboratory  Jinan Shandong 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