{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T04:26:12Z","timestamp":1745209572188},"reference-count":16,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2010,9,7]],"date-time":"2010-09-07T00:00:00Z","timestamp":1283817600000},"content-version":"vor","delay-in-days":5912,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Trans Emerging Tel Tech"],"published-print":{"date-parts":[[1994,7]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper describes the structure of a signal interpolator chip to be used in medium\u2010to\u2010high data rate digital modems, based on the so\u2010called \u201cSystolic Macrocells\u201d design style. In particular, we focus on a third\u2010order polynomial interpolation algorithm, as a good trade\u2010off between the contrasting needs of high accuracy and low complexity\/cost. We also present a concise description of the architecture of the chip through a functional description of the main basic systolic macrocells it is composed of. Despite the apparent complexity of the architecture, the basic cells of each bit\u2010level systolic array are remarkably simple and homogeneous: they are mainly composed by delays and summing elements such as full and half adders, so that their realization does not represent a difficult design task. The interpolator chip has been completely laid out assuming a 1.2 \u03bc m CMOS technology and occupies a silicon area of 5 \u00d7 4.5 mm<jats:sup>2<\/jats:sup>, pad included. In particular, we envisage an operating clock frequency of 70 MHz, so that the chip can process sequences of 8 bit words at the rate of 17.5 MSamples\/s with a power supply requirement of less than 0.5 W.<\/jats:p>","DOI":"10.1002\/ett.4460050409","type":"journal-article","created":{"date-parts":[[2010,9,14]],"date-time":"2010-09-14T19:10:32Z","timestamp":1284491432000},"page":"475-482","source":"Crossref","is-referenced-by-count":3,"title":["VLSI implementation of a signal interpolator chip for high\u2010speed all\u2010digital data modems"],"prefix":"10.1002","volume":"5","author":[{"given":"Marco","family":"Luise","sequence":"first","affiliation":[]},{"given":"Roberto","family":"Roncella","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2010,9,7]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/26.31179"},{"key":"e_1_2_1_3_2","first-page":"998","article-title":"Interpolation in digital modems","volume":"41","author":"Gardner F. M.","year":"1993","journal-title":"Part I: Fundamentals, \u201cIEEE Trans. Commun.\u201d"},{"key":"e_1_2_1_4_2","first-page":"501","article-title":"Interpolation in digital modems","volume":"41","author":"Erup L.","year":"1993","journal-title":"Part II: Implementation And Performance, \u201cIEEE Trans. Commun.\u201d"},{"key":"e_1_2_1_5_2","volume-title":"The theory and practice of modem design","author":"Bingham J. A. C.","year":"1988"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1987.13872"},{"key":"e_1_2_1_7_2","doi-asserted-by":"crossref","unstructured":"J. V.McCanny J. G.McWhirter: Some systolic array developments in the united kingdom. \u201cComputer\u201d July1987 p.51\u201363.","DOI":"10.1109\/MC.1987.1663620"},{"key":"e_1_2_1_8_2","volume-title":"Numerical methods for scientists and engineers","author":"Hamming R.","year":"1973"},{"key":"e_1_2_1_9_2","volume-title":"Essentials of Pad\u00e8 approximants","author":"Baker G. A.","year":"1975"},{"key":"e_1_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1987.1165023"},{"key":"e_1_2_1_11_2","doi-asserted-by":"publisher","DOI":"10.1016\/0165-1684(83)90013-0"},{"key":"e_1_2_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1973.9150"},{"key":"e_1_2_1_13_2","unstructured":"C. W.Farrow:A continuously variable digital delay element. IEEE Int. Symposium on Circuit and Systems Espoo Finland June1988."},{"key":"e_1_2_1_14_2","volume-title":"Un nuovo stile di progetto per sistemi integrati VLSI dedicati all'elaborazione numerica del segnali","author":"Roncella R.","year":"1988"},{"key":"e_1_2_1_15_2","doi-asserted-by":"publisher","DOI":"10.1002\/ett.4460010604"},{"key":"e_1_2_1_16_2","first-page":"17","article-title":"Application of systolic macrocell\u2010based VLSI design style to the design of a single\u2010chip high performance FIR filter","volume":"138","author":"Roncella R.","year":"1991","journal-title":"\u201cIEE Proc., Part G\u201d"},{"key":"e_1_2_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/29.17566"}],"container-title":["European Transactions on Telecommunications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fett.4460050409","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/ett.4460050409","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,24]],"date-time":"2023-10-24T04:02:12Z","timestamp":1698120132000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/ett.4460050409"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,7]]},"references-count":16,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1994,7]]}},"alternative-id":["10.1002\/ett.4460050409"],"URL":"https:\/\/doi.org\/10.1002\/ett.4460050409","archive":["Portico"],"relation":{},"ISSN":["1124-318X","1541-8251"],"issn-type":[{"value":"1124-318X","type":"print"},{"value":"1541-8251","type":"electronic"}],"subject":[],"published":{"date-parts":[[1994,7]]}}}