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In this paper, to obtain both more accurate output frequencies with a few stages and a higher speed acquisition time, we propose two methods for improving<jats:italic>NSCS<\/jats:italic>switching operation. First, by allowing the<jats:italic>NSCS<\/jats:italic>output frequency to be variable a large range of choices in the division ratios becomes available in the<jats:italic>NSCS<\/jats:italic>. The proposed synthesizer has the output frequency of deviation within 0.0003 ppm when the 3\u2010stage cycle swallower is employed. Second, by temporarily increasing the expected amount of the variation in the output frequency, the acquisition time of the<jats:italic>NSCS<\/jats:italic>synthesizer can be improved. Experimental results confirm that the proposed technique results in a shortened acquisition time.<\/jats:p>","DOI":"10.1002\/ett.4460070203","type":"journal-article","created":{"date-parts":[[2008,9,12]],"date-time":"2008-09-12T11:42:29Z","timestamp":1221219749000},"page":"125-131","source":"Crossref","is-referenced-by-count":0,"title":["Improved performance of fast acquisition PLL synthesizer with<i>N<\/i>\u2010stage cycle swallower"],"prefix":"10.1002","volume":"7","author":[{"given":"Takahiko","family":"Saba","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Duk\u2010Kyu","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinsaku","family":"Mori","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2008,9,12]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/26.20101"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TAU.1971.1162151"},{"key":"e_1_2_1_4_2","doi-asserted-by":"crossref","unstructured":"V.Reinhardt K.Gould K.McNab M.Bustamante A short survey of frequency synthesizer techniques. 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