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This is in contrast to common practice where these tasks are performed by sequentially operating processors. Our advantage is that we operate fully on soft values for input and output, similar to what is done in 'turbo' decoding. However, we do not have explicit iterations because the networks float freely in continuous time. The decoder has almost no latency in time because we are only restricted by the time constants from the parasitic RC values of integrated circuits. Simulation results for several simple examples are shown which, in some cases, achieve the performance of a conventional MAP detector. For more complicated codes we indicate promising solutions with more complex analog networks based on the simple ones. Furthermore, we discuss the principles of the analog VLSI implementation of these networks.<\/jats:p>","DOI":"10.1002\/ett.4460100610","type":"journal-article","created":{"date-parts":[[2008,9,12]],"date-time":"2008-09-12T14:58:57Z","timestamp":1221231537000},"page":"659-680","source":"Crossref","is-referenced-by-count":38,"title":["Decoding and Equalization with Analog Non\u2010linear Networks"],"prefix":"10.1002","volume":"10","author":[{"given":"Joachim","family":"Hagenauer","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elke","family":"Offer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cyril","family":"M\u00e9asson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthias","family":"M\u00f6rz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2008,9,12]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"crossref","unstructured":"C.Bcrrou A.Glavieux andP.Thitimajshima Near Shannon limit error\u2010correcting coding and decoding: Turbo\u2010codes(I). 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Symp. on Turbo Codes & Related Topics Brest France pages12\u201325 Sept.1997."},{"key":"e_1_2_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/49.661110"},{"key":"e_1_2_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/49.661103"},{"key":"e_1_2_1_19_2","unstructured":"F.Kschischang B.Frey andH.\u2010A.Loeliger Factor graphs and the sum\u2010product algorithm.Submitted to IEEE Trans. Inform. Theory July 1998. Available athttp:\/\/www.comm.utoronto.ca\/frank\/factor\/."},{"key":"e_1_2_1_20_2","unstructured":"H.\u2010A.Loeliger M.Helfenstein F.Lustenberger andF.Tarkoey Iterative sum\u2010product decoding with analog VLSI. InProc. ISIT '98 Cambridge MA USA page146 1998."},{"key":"e_1_2_1_21_2","unstructured":"H.\u2010A.Loeliger F.Lustenberger M.Helfenstein andF.Tarkoey Probability propagation in analog VLSI. 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