{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T06:10:48Z","timestamp":1697955048532},"reference-count":10,"publisher":"Wiley","issue":"10","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":7749,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1986,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper describes the architectural evaluation of a universal host computer MUNAP in terms of: (1) nonnumerical capability; (ii) multiprocessor parallelism; and (iii) flexibility of the two\u2010level microprogramming scheme, based on the experimental results.<\/jats:p><jats:p>The findings of the dynamic evaluation are summarized as follows.<\/jats:p><jats:p>(i) The divide and concatenate unit is especially useful for decoding machine instructions and manipulating tags in high\u2010level language machines so that the number of execution steps is decreased 30\u201340 percent. The bit operation unit is useful for numerical processing which frequently utilizes priority encoding. This provides a reduction in execution steps of 15 percent. In the shuffle exchange network, 16, 32, and 48\u2010bit circular shifts and broadcasts are used effectively for data transfers between processor units and serial operations.<\/jats:p><jats:p>(ii) The average numbers of active processor units are 3.6 \u2010 3.8 for such numerical computations as Fast Fourier Transform, and 2.1 to 2.5 for emulations of a wide variety of high\u2010level languages.<\/jats:p><jats:p>(iii) In the two\u2010level microprogramming scheme, the allocation ratio of the nanoprogram memory increases due to word size optimization of nanoprogram memory so that 80 \u2010 90 percent of it is used for large\u2010scale microprograms.<\/jats:p>","DOI":"10.1002\/scj.4690171008","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T10:51:54Z","timestamp":1183805514000},"page":"78-87","source":"Crossref","is-referenced-by-count":0,"title":["Architectural evaluation of a universal host computer munap"],"prefix":"10.1002","volume":"17","author":[{"given":"Katsuhiro","family":"Yamazaki","sequence":"first","affiliation":[]},{"given":"Hiroyuki","family":"Kanai","sequence":"additional","affiliation":[]},{"given":"Takanobu","family":"Baba","sequence":"additional","affiliation":[]},{"given":"Kenzo","family":"Okuda","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","first-page":"1329","volume-title":"Dynamic Architecture, bit","author":"Aiso H.","year":"1980"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223634"},{"key":"e_1_2_1_4_2","first-page":"2","article-title":"Static Characteristics of Microprograms in a Microprocessor (PULCE)","volume":"65","author":"Furuya T.","year":"1982","journal-title":"Trans. I.E.C.E., Japan"},{"key":"e_1_2_1_5_2","first-page":"11","article-title":"Emulations on Some Language Processors on a Universal Host Computer MUNAP","volume":"65","author":"Shibayama K.","year":"1982","journal-title":"Trans. I.E.C.E., Japan"},{"issue":"6","key":"e_1_2_1_6_2","first-page":"518","article-title":"Architecture of a Two\u2010Level Microprogrammed Computer MUNAP","volume":"64","author":"Baba T.","year":"1986","journal-title":"Trans. I.E.C.E., Japan"},{"key":"e_1_2_1_7_2","first-page":"6","article-title":"Non\u2010numeric Processing by a Two\u2010Level Microprogrammed Computer MUNAP","volume":"64","author":"Baba T.","year":"1986","journal-title":"Trans. I.E.C.E., Japan"},{"key":"e_1_2_1_8_2","first-page":"1","article-title":"Development of a System Description Language for a Two\u2010Level Microprogrammed Computer MUNAP","volume":"67","author":"Yamazaki K.","year":"1984","journal-title":"Trans. I.E.C.E., Japan"},{"key":"e_1_2_1_9_2","first-page":"623","article-title":"Software Testing System Supported by a Tagged Architecture","volume":"4","author":"Sano T.","year":"1984","journal-title":"IPSJ 28th National Convention Record"},{"key":"e_1_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"e_1_2_1_11_2","doi-asserted-by":"crossref","unstructured":"T.Baba M.Ikeda K.YamazakiandK.Okuda. Compaction of Two\u2010Level Microprograms for a Multiprocessor Computer 7th Annu. Workshop on Microprogramming ACM and IEEE Preprints pp.95\u2013104(1984).","DOI":"10.1145\/384281.808219"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690171008","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690171008","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T06:10:43Z","timestamp":1697868643000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690171008"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986,1]]},"references-count":10,"journal-issue":{"issue":"10","published-print":{"date-parts":[[1986,1]]}},"alternative-id":["10.1002\/scj.4690171008"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690171008","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1986,1]]}}}