{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T06:41:25Z","timestamp":1697956885576},"reference-count":10,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":7384,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1987,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>With the advance of scale and integrity of LSIs, several kinds of CAD systems are being developed and introduced to design verification and mask pattern generation for mask pattern data as a means of shortening the design time. The processings common to these CAD systems are pattern logical operations. This paper proposes effective and fast pattern operation algorithms for large\u2010scale data containing patterns of any angle: the virtual slit method and limited searching algorithm. The virtual slit method is a logical operation algorithm performing concurrently the three processings, intersection\u2010point calculation, slit division, and logical processing which have been done independently in old algorithms. The limited searching algorithm is a highspeed intersection\u2010point calculation algorithm indispensable for diagonal figures. The time complexity of both methods is theoretically O(N<jats:sub>v<\/jats:sub>) log N<jats:sub>v<\/jats:sub>) where N<jats:sub>v<\/jats:sub> is the number of input vectors. For manufactured LSI mask data, we obtained the result for the time complexity based on estimation by program execution which can be approximated by O(N<jats:sub>v<\/jats:sub>).<\/jats:p>","DOI":"10.1002\/scj.4690180210","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T13:29:43Z","timestamp":1183814983000},"page":"98-108","source":"Crossref","is-referenced-by-count":0,"title":["A concurrent pattern operation algorithm for VLSI mask data"],"prefix":"10.1002","volume":"18","author":[{"given":"Akira","family":"Tsukizoe","sequence":"first","affiliation":[]},{"given":"Tokinori","family":"Kozawa","sequence":"additional","affiliation":[]},{"given":"Jun'Ya","family":"Sakemi","sequence":"additional","affiliation":[]},{"given":"Chihei","family":"Miura","sequence":"additional","affiliation":[]},{"given":"Tatsuki","family":"Ishii","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","unstructured":"K.Yoshida T.Mitsuhashi Y.Nakada T.Chiba K.OgitaandS.Nakatsuka.A Layout Checking System for Large\u2010Scale Integrated Circuits Proc. 14th DA Conf. pp.322\u2013330(June1977)."},{"key":"e_1_2_1_3_2","doi-asserted-by":"crossref","unstructured":"P.Wilcox H.RombeekandD. M.Caughey.Design Rule Verification Based on One\u2010Dimensional Scans Proc. 15th DA Conf. pp.285\u2013289(June1978).","DOI":"10.1109\/DAC.1978.1585186"},{"key":"e_1_2_1_4_2","doi-asserted-by":"crossref","unstructured":"C. R.McCaw.Unified Shapes Checker \u2014 A Checking Tool for LSI Proc. 16th DA Conf. pp.81\u201387(June1979).","DOI":"10.1109\/DAC.1979.1600092"},{"key":"e_1_2_1_5_2","unstructured":"H. S.BairdandY. E.Cho.An Artwork Design Verification System Proc. 12th DA Conf. pp.414\u2013420(June1975)."},{"key":"e_1_2_1_6_2","unstructured":"H. S.Baird.Fast Algorithms for LSI Artwork Analysis Proc. 14th DA Conf. pp.303\u2013311(June1977)."},{"key":"e_1_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1972.tb02671.x"},{"key":"e_1_2_1_8_2","doi-asserted-by":"crossref","unstructured":"B. W.LindsayandB. T.Preas.Design Rule Checking and Analysis of IC Mask Designs Proc. 13th DA Conf. pp.301\u2013308(June1976).","DOI":"10.1145\/800146.804829"},{"issue":"9","key":"e_1_2_1_9_2","first-page":"611","article-title":"An Algorithm on Graphical Manipulation of LSI Mask Pattern","volume":"63","author":"Kawanishi Nishide","year":"1980","journal-title":"Trans. I. E. C. E., Japan"},{"key":"e_1_2_1_10_2","doi-asserted-by":"crossref","unstructured":"I.DobesandR.Byrd.The Automatic Recognition of Silicon Gate Transistor Geometries Proc. 13th DA Conf. pp.327\u2013335(June1976).","DOI":"10.1145\/800146.804832"},{"key":"e_1_2_1_11_2","doi-asserted-by":"crossref","unstructured":"T.Kozawa A.Tsukizoe J.Sakemi C.MiuraandT.Ishii.A Concurrent Pattern Operation Algorithm for VLSI Mask Data Proc. 18th DA Conf. pp.563\u2013570(June1981).","DOI":"10.1109\/DAC.1981.1585411"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690180210","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690180210","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T07:28:17Z","timestamp":1697873297000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690180210"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,1]]},"references-count":10,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1987,1]]}},"alternative-id":["10.1002\/scj.4690180210"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690180210","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1987,1]]}}}