{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T06:10:49Z","timestamp":1697955049862},"reference-count":15,"publisher":"Wiley","issue":"9","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":7384,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1987,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper considers a programmable logic unit (PLU) which is a computing\u2010in\u2010memory device with stepwise programmable computing logics and the data transmission lines\/buses, and discusses its operational characteristics. The PLU is combined with the memory device in a Neumann\u2010type computer with a great number of computing logics. From the viewpoint of Flynn's classification in the Neumann\u2010type computer, we consider the level\u20101 PLU and the level\u20102 PLU as structures for the PLU, and discuss their configurations in detail. First, we discuss the mapping method and the number of steps for the program of the mathematical expression. It is shown that the PLU can map directly the program written in the inverse\u2010Poland notion and that the connection lines\/buses can easily be assigned. Second, we discuss the comparison between the computing time of the computer with the PLU and the processing time of the Neumann\u2010type computer. It is shown that the computer with the PLU is several times faster than the Neumann\u2010type computer in processing the program. On the other hand, it is seen that the level\u20102 PLU with the distributed buses is suited to the general\u2010purpose computer, although the processing speed is somewhat low.<\/jats:p>","DOI":"10.1002\/scj.4690180904","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T14:22:12Z","timestamp":1183818132000},"page":"31-43","source":"Crossref","is-referenced-by-count":0,"title":["Characteristics of a programmable logic unit"],"prefix":"10.1002","volume":"18","author":[{"given":"Takahiko Murayama, Associate","family":"Member","sequence":"first","affiliation":[]},{"given":"Hidekazu","family":"Yamada","sequence":"additional","affiliation":[]},{"given":"Tadao","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"Yoshiharu","family":"Shigei","sequence":"additional","affiliation":[]},{"given":"Yoshio","family":"Yoshioka","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","unstructured":"D. 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