{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T20:45:10Z","timestamp":1698007510101},"reference-count":9,"publisher":"Wiley","issue":"12","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":7384,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1987,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper considers the fast\u2010Fourier transform (FFT) which processes a large amount of data, such as image. As a structure for the one\u2010dimensional FFT processor, aiming at eliminating some restrictions in VLSI design, the constant\u2010geometry type FFT algorithm and the bit\u2010serial pipeline floating\u2010point arithmetic are discussed. The major results are as follows. (1) Using the constant\u2010geometry algorithm, the memory elements to perform the rearrangement characteristic to FFT can be realized by a uniform structure and uniform control scheme throughout the stages. The memory element for <jats:italic>N<\/jats:italic>\u2010point FFT can be constructed as a simple and regular structure using 2 of <jats:italic>N<\/jats:italic>\/2\u2010stage shift\u2010registers. (2) The multiplication cell with code extender, the serial structure of normalization circuit and the shifter, and the parallel operation covering a longer length than the input word length are employed. By those schemes, the pipeline operation of floatingpoint arithmetic is realized without a guard bit. By this scheme, the restriction in VLSI using the butterfly elements can be reduced drastically. (3) As an additional effect of the regular structure of the memory element, the automatic defecttolerant operation is made possible, using the effective <jats:italic>k<\/jats:italic>\u2010out\u2010of\u2010<jats:italic>n<\/jats:italic> redundant structure and the self\u2010testing. By this scheme, the restriction for the VLSI chip\u2010area can be reduced when the number of sampling points is increased. (4) The one\u2010dimensional FFT processor can be realized as a modular structure, which is a cascade connection of two kinds of VLSI, i. e., butterfly element and the memory elements.<\/jats:p>","DOI":"10.1002\/scj.4690181203","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T13:29:42Z","timestamp":1183814982000},"page":"18-28","source":"Crossref","is-referenced-by-count":1,"title":["A VLSI architecture for pipeline fft processor"],"prefix":"10.1002","volume":"18","author":[{"given":"Yukio","family":"Takahashi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satoshi","family":"Sekine","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","first-page":"644","article-title":"An LSI chip set for DSP hardware implementation","volume":"81","author":"Kanemasa A.","year":"1981","journal-title":"ICASSP"},{"issue":"17","key":"e_1_2_1_3_2","first-page":"5","article-title":"A VLSI delay commutator for FFT implementation","volume":"84","author":"Swartzlander E.","year":"1984","journal-title":"ISSCC"},{"issue":"7","key":"e_1_2_1_4_2","first-page":"725","article-title":"Construction of ultra\u2010highspeed pipeline FFT processor","volume":"21","author":"Kameyama A.","year":"1985","journal-title":"Proc. Soc. Instr. Contr. Eng."},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"e_1_2_1_6_2","first-page":"575","volume-title":"Theory and Application of Digital Signal Processing","author":"Rabiner L. R.","year":"1975"},{"key":"e_1_2_1_7_2","unstructured":"S.SekineandY.Takahashi.One\u2010dimensional FFT processor with modulator structure 29th Nat. Conv. Inf. Proc. Soc. Jap. pp.131\u2013132(1984)."},{"key":"e_1_2_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676458"},{"key":"e_1_2_1_9_2","article-title":"Construction of bit\u2010serial floating\u2010point multiplier","volume":"482","author":"Sekine S.","year":"1985","journal-title":"Nat. Conv. I. E. C. E., Japan"},{"key":"e_1_2_1_10_2","first-page":"418","volume-title":"Two's complement pipeline multipliers","author":"Lyon R. F.","year":"1976"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690181203","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690181203","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T03:50:51Z","timestamp":1697860251000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690181203"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1987,1]]},"references-count":9,"journal-issue":{"issue":"12","published-print":{"date-parts":[[1987,1]]}},"alternative-id":["10.1002\/scj.4690181203"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690181203","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1987,1]]}}}