{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:53:52Z","timestamp":1759146832904},"reference-count":14,"publisher":"Wiley","issue":"6","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":6867,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1988,6]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>With the recent development of high\u2010density logical circuits with complex functions, a problem is produced in the long time for the functional testing. One method to cope with this problem is to employ builtin testing, which is one of the designs for testability. The method includes the testing circuit in the IC chip (the circuit under test), and testing is performed by the chip itself to decide whether or not the function is normal. We have already proposed new built\u2010in testing, which can test concurrently all memory cells on a word\u2010line. The pattern\u2010sensitive fault is one of the faults which have been difficult to detect. This paper applies the previously proposed method to such a fault, and presents the result. Using the method in this paper, testing can be performed by the near\u2010optimal test sequence with the complexity of 302<jats:italic>N<\/jats:italic><jats:sup>1\/2<\/jats:sup>, which is a drastic decrease compared with other testing methods reported to date. The testing circuit can easily be constructed using counters and shift\u2010registers. The hardware overhead as evaluated by the equivalent number of gates is almost negligible when the memory capacity is increased.<\/jats:p>","DOI":"10.1002\/scj.4690190605","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T15:16:51Z","timestamp":1183821411000},"page":"50-62","source":"Crossref","is-referenced-by-count":1,"title":["Built\u2014in concurrent testing for semiconductor random access memories by concurrently testing cells on a word\u2010line"],"prefix":"10.1002","volume":"19","author":[{"given":"Yukiya","family":"Miura","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideo","family":"Tamamoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuichi","family":"Narita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224182"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1977.217778"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675556"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675601"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/356914.356916"},{"key":"e_1_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12531"},{"key":"e_1_2_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051391"},{"key":"e_1_2_1_9_2","volume-title":"Built\u2010in testing of memory chips, Technical Report, No. EE8335","author":"Kinoshita K.","year":"1983"},{"key":"e_1_2_1_10_2","article-title":"Built\u2010in testing of memory by compact testing","volume":"11","author":"Kinoshita K.","year":"1981","journal-title":"Tech. Rep. Elect. Dev."},{"key":"e_1_2_1_11_2","unstructured":"M.NicolaidisAn efficient built\u2010in self\u2010test scheme for functional test of embedded RAMs Proc.15th Fault\u2010Tolerant Computing pp.118\u2013123(June1985)."},{"key":"e_1_2_1_12_2","unstructured":"Z.SunandL. T.Wang. Self\u2010testing of embedded RAMs 1984 I.E.E.E. Test Conference pp.148\u2013156(1984)."},{"issue":"11","key":"e_1_2_1_13_2","first-page":"1556","article-title":"Built\u2010in testing scheme for IC memories by considering address decoder and cell array separately","volume":"69","author":"Tamamoto H.","year":"1986","journal-title":"Trans. (D) I.E.C.E., Japan"},{"issue":"10","key":"e_1_2_1_14_2","first-page":"1416","article-title":"Built\u2010in testing for functional testing in semiconductor random access memorym","volume":"69","author":"Miura Y.","year":"1986","journal-title":"Trans. (D) I.E.C.E., Japan"},{"key":"e_1_2_1_15_2","unstructured":"S. M.ThatteandJ. A.Abraham. Testing of semiconductor random access memories Proc. 7th Fault\u2010Tolerant Computing pp.81\u201387(June1977)."}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690190605","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690190605","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T09:19:09Z","timestamp":1697966349000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690190605"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1988,6]]},"references-count":14,"journal-issue":{"issue":"6","published-print":{"date-parts":[[1988,6]]}},"alternative-id":["10.1002\/scj.4690190605"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690190605","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1988,6]]}}}