{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,23]],"date-time":"2023-10-23T05:01:07Z","timestamp":1698037267305},"reference-count":6,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":6653,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1989,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper proposes to use a multiple\u2010valued (<jats:italic>p<\/jats:italic>\u2010valued) input, 2\u2010valued output logical element ((<jats:italic>p<\/jats:italic>, 2)\u2010logical element) for the construction of a 2\u2010valued ULM (Universal Logic Module). The (<jats:italic>p<\/jats:italic>, 2)\u2010logical element can conveniently be programmed to work as an expected 2\u2010valued logical function by appropriately selecting two input values among <jats:italic>p<\/jats:italic> values. The (<jats:italic>p<\/jats:italic>, 2)\u2010logical element as a ULM also has some preferable points such that the interconnections between ULM's can be decreased in VLSI, compared with the ULM in usual 2\u2010valued logic.<\/jats:p>","DOI":"10.1002\/scj.4690200107","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T16:51:39Z","timestamp":1183827099000},"page":"65-73","source":"Crossref","is-referenced-by-count":0,"title":["Multivalued input, two\u2010valued output logical element as a two\u2010valued universal logic module"],"prefix":"10.1002","volume":"20","author":[{"given":"Takahiro","family":"Haga","sequence":"first","affiliation":[]},{"given":"Teruo","family":"Fukumura","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","volume-title":"Recent Developments in Switching Theory","author":"Mukhopadhyay A.","year":"1971"},{"key":"e_1_2_1_3_2","volume-title":"Theory and Design of Switching Circuits","author":"Friedman A. D.","year":"1975"},{"key":"e_1_2_1_4_2","doi-asserted-by":"crossref","DOI":"10.1016\/0165-1684(85)90052-0","volume-title":"Spectral Techniques in Digital Logic","author":"Hurst S. L.","year":"1985"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.223829"},{"key":"e_1_2_1_6_2","volume-title":"Usage of PLA","author":"Nanya T.","year":"1978"},{"key":"e_1_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1970.222906"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690200107","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690200107","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T13:10:11Z","timestamp":1697980211000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690200107"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,1]]},"references-count":6,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1989,1]]}},"alternative-id":["10.1002\/scj.4690200107"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690200107","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1989,1]]}}}