{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T11:41:07Z","timestamp":1697974867222},"reference-count":22,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":6653,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1989,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>With the progress of high\u2010density information handling technology, multiple\u2010valued logic is considered interesting. Studies have been made on the applications to the high\u2010density VLSI and the optimally multiple\u2010valued information processing systems. This paper considers the use of a CMOS multiple\u2010valued output gate, and proposes an implementation of the multiple\u2010valued logic circuit, which is suited to the integration from the viewpoints of the integration density and the power consumption. The CMOS multiple\u2010valued output gate produces a multiple\u2010valued output from the predetermined number (<jats:italic>n<\/jats:italic> \u2010 1 for <jats:italic>n<\/jats:italic>\u2010valued case) of binary inputs. Compared with similar multiple\u2010level output circuits proposed up to now, the gate has the feature of simple structure and easy correspondence to arbitrary <jats:italic>n<\/jats:italic>\u2010valued function. In the design of the multiple\u2010valued logic circuit by the proposed method, the inputs to the multiple\u2010valued output gate are determined first from the required multiple\u2010valued output. Then the logic circuit satisfying the inputs is constructed from the literal circuit with multiple\u2010valued inputs and binary logic circuits. Design examples by the proposed method are presented. It is shown especially for the arbitrary <jats:italic>n<\/jats:italic>\u2010valued case that the design is simplified since the inputs to the multiple\u2010valued output gate can be represented in the general form. Several rules for deriving the general form are described. Finally, it is made possible to implement the multiple\u2010valued logic circuit, which is simple and suited to integration.<\/jats:p>","DOI":"10.1002\/scj.4690200207","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T17:30:17Z","timestamp":1183829417000},"page":"67-77","source":"Crossref","is-referenced-by-count":0,"title":["An implementation of multiple\u2010valued logic circuit with cmos multiple\u2010valued output gates"],"prefix":"10.1002","volume":"20","author":[{"given":"Izumi","family":"Sakata","sequence":"first","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052114"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676727"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224138"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674783"},{"key":"e_1_2_1_6_2","unstructured":"J. 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(D), I.E.C.E., Japan"},{"key":"e_1_2_1_15_2","unstructured":"WatanabeandMatsumoto.Implementation of quaternary logic circuit using CMOS. 4th Multivalued Logic Forum (July1985)."},{"key":"e_1_2_1_16_2","unstructured":"Horie KameyamaandHiguchi.Optimal design of quaternary complementary path\u2010gate network. 7th Multivalued Logic Forum (Jan.1987)."},{"issue":"9","key":"e_1_2_1_17_2","first-page":"1064","article-title":"NMOS integrated circuit using four\u2010valued T gate","volume":"67","author":"Kameyama Higuchi","year":"1984","journal-title":"Trans. (D), I.E.C.E., Japan"},{"key":"e_1_2_1_18_2","article-title":"Proposal for ternary waveform\u2010shaping circuit using insulated\u2010gate FET","volume":"77","author":"Sakata I.","year":"1977","journal-title":"I.E.C.E., Japan"},{"key":"e_1_2_1_19_2","unstructured":"Kawabata YoshidaandI.Sakata.Ternary T\u2010gate logic circuit using C\u2010MOSFET. Joint Conv. Tokai. Chap. 446 (1980)."},{"key":"e_1_2_1_20_2","article-title":"Implementation of ternary logic circuit using ternary CMOS output circuit","volume":"596","author":"Sakata I.","year":"1985","journal-title":"Nat. Conv. Gen., I.E.C.E., Japan"},{"issue":"3","key":"e_1_2_1_21_2","first-page":"412","article-title":"Design of ternary memory circuit for MOC\u2010IC","volume":"68","author":"Sakata I.","year":"1985","journal-title":"I.E.C.E., Japan"},{"key":"e_1_2_1_22_2","unstructured":"Suteja I.Sakata T.MuranakaandS.Imanishi.Implementation of ternary logic circuit using CMOS ternary output gate II. Joint Conv. Kansai Chap. G303 (1985)."},{"key":"e_1_2_1_23_2","unstructured":"I.Sakata.Implementation of four\u2010valued logic circuit using CMOS four\u2010valued output gate. Joint Conv. Tokai Chap. 252 (1985)."}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690200207","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690200207","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T01:53:33Z","timestamp":1697939613000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690200207"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,1]]},"references-count":22,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1989,1]]}},"alternative-id":["10.1002\/scj.4690200207"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690200207","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1989,1]]}}}