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This idea formed the basis for developing a new simulation processor, the \u201cSP\u201d. The SP is a system dedicated for simulation which performs parallel processing using up to 64 gate processors (GP). Using a newly devised pipeline control for each processor delivers high\u2010speed and inexpensive simulation. By combining processors with a high\u2010speed switch called ET, the degradation of processing speed due to the delay of information transmission in parallel processing can be prevented. The desired goal was achieved with the construction of the SP, a logic circuit with 4 million gates in which 32 Mbytes of memory could be simulated at high speed.<\/jats:p>","DOI":"10.1002\/scj.4690200407","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T17:37:28Z","timestamp":1183829848000},"page":"71-79","source":"Crossref","is-referenced-by-count":0,"title":["Simulation processor \u201cSP\u201d"],"prefix":"10.1002","volume":"20","author":[{"given":"Hiroshi","family":"Yamada","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fumiyasu","family":"Hirose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junichi","family":"Niitsuma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tatsuya","family":"Shindo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1984.5005647"},{"issue":"10","key":"e_1_2_1_3_2","first-page":"1144","article-title":"CAD\u2010dedicated system","volume":"25","author":"Ohmori K.","year":"1984","journal-title":"Inf. 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