{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,22]],"date-time":"2023-10-22T12:42:48Z","timestamp":1697978568385},"reference-count":8,"publisher":"Wiley","issue":"12","license":[{"start":{"date-parts":[[2007,9,5]],"date-time":"2007-09-05T00:00:00Z","timestamp":1188950400000},"content-version":"vor","delay-in-days":6821,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1989,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Associative memories and associaLive computer systems with high\u2010speed processing capability have been increasingly required in the real\u2010time application domains, such as File Maintenance, Pattern Recognition, Translation, Artificial Intelligence, and so on. This paper presents a design of high\u2010performance multiple\u2010valued associative memory which can perform ultrahigh\u2010speed processing at low cost.<\/jats:p><jats:p>In the proposed method, the correlation between input pattern and memorized pattern is represented directly as multiple\u2010valued information, so that associative processing is performed efficiently by multiple\u2010valued operations. Based on a complete parallel processing architecture with multiple\u2010valued digit\u2010cell, each correlation can be calculated in parallel.<\/jats:p><jats:p>In hardware implementation of a single digit\u2010cell, two kinds of new devices are proposed: the SOS transistor and the floating\u2010gate MOS transistor. By using these devices, multiple\u2010valued operators and multiple\u2010valued memories for the associative memory can be realized efficiently at the device level. It is demonstrated that compared with the corresponding binary implementation the proposed associative memory is very compact.<\/jats:p>","DOI":"10.1002\/scj.4690201203","type":"journal-article","created":{"date-parts":[[2009,11,19]],"date-time":"2009-11-19T22:35:52Z","timestamp":1258670152000},"page":"23-33","source":"Crossref","is-referenced-by-count":0,"title":["Design of a Multiple\u2010Valued Associative Memory"],"prefix":"10.1002","volume":"20","author":[{"given":"Takahiro","family":"Hanyu","sequence":"first","affiliation":[]},{"given":"Tatsuo","family":"Higuchi","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,9,6]]},"reference":[{"key":"e_1_2_1_2_2","volume-title":"Association\u2014A model for associative memory and intelligent information processing","author":"Nakano K.","year":"1979"},{"issue":"10","key":"e_1_2_1_3_2","first-page":"743","article-title":"Associative processor ARES","volume":"61","author":"Ichikawa","year":"1978","journal-title":"Trans. (D), I.E.C.I.E., Japan"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1978.1675200"},{"issue":"5","key":"e_1_2_1_5_2","first-page":"667","article-title":"Design and implementation of an nMOS image processor based on quaternary logic","volume":"69","author":"Hanyu T.","year":"1986","journal-title":"Trans, (D), I.E.C.I.E., Japan"},{"issue":"2","key":"e_1_2_1_6_2","first-page":"493","article-title":"Design of a quaternary gate array for high\u2010speed pattern matching","volume":"70","author":"Hanyu T.","year":"1987","journal-title":"Trans. (D), I.E.C.I.E., Japan"},{"key":"e_1_2_1_7_2","unstructured":"T.Hanyu M.Kameyama andT.Higuchi Design of a multiple\u2010valued super chip for intelligent information processing. Papers of Technical Group on Circuits and Systems I.E.C.I.E. Japan CAS87\u201021 (May1987)."},{"key":"e_1_2_1_8_2","volume-title":"Theory of Operation of MOS Transistor","author":"Takeishi Y.","year":"1984"},{"key":"e_1_2_1_9_2","doi-asserted-by":"crossref","unstructured":"W. S.Johnsonet al A 16\u2010kbyte electrically erasable nonvolatile memory. ISSCC'80 Dig. Tech. Papers pp.152\u2013153(Feb.1980).","DOI":"10.1109\/ISSCC.1980.1156030"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690201203","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690201203","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,21]],"date-time":"2023-10-21T16:32:48Z","timestamp":1697905968000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690201203"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,1]]},"references-count":8,"journal-issue":{"issue":"12","published-print":{"date-parts":[[1989,1]]}},"alternative-id":["10.1002\/scj.4690201203"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690201203","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1989,1]]}}}