{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T17:10:13Z","timestamp":1737220213802,"version":"3.33.0"},"reference-count":19,"publisher":"Wiley","issue":"11","license":[{"start":{"date-parts":[[2007,3,22]],"date-time":"2007-03-22T00:00:00Z","timestamp":1174521600000},"content-version":"vor","delay-in-days":6289,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1990,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper discusses the test\u2010generation circuit which automatically generates a test pattern for a combinational circuit. The test\u2010generation circuit is designed so that two algorithms of automatic test generation and fault simulation can be executed by the circuit. The test pattern for the circuit under test is generated at a high speed by simulating the operation of the test\u2010generation circuit using the dedicated logic simulation machine SP. As a result of performance evaluation for the well known benchmark circuits, the test\u2010generation circuit was constructed with eleven times the number of SP elements on the average compared with the circuit under test. By a simulation using only one SP processor, the operation of the test\u2010generation circuit could be simulated at 6 kHz on the average. Thus, it is seen that the test pattern for the circuit under test can be generated with a high fault coverage with a speed surpassing the software on a large\u2010scale computer. The method proposed herein is to apply effectively the architecture of the dedicated machine for a high\u2010speed logic simulation to the search problem such as test generation. Thus, the validity of the idea was verified.<\/jats:p>","DOI":"10.1002\/scj.4690211102","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T18:44:33Z","timestamp":1183833873000},"page":"12-20","source":"Crossref","is-referenced-by-count":0,"title":["A high\u2010speed test\u2010generation method using a test generation circuit"],"prefix":"10.1002","volume":"21","author":[{"given":"Fumiyasu","family":"Hirose","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koichiro","family":"Takayama","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nobuaki","family":"Kawato","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,22]]},"reference":[{"key":"e_1_2_1_2_2","unstructured":"K.KinoshitaandH.Fujiwara.Fault Diagnosis of Digital Circuit (1) pp.214\u2013219. Kogaku Tosho Co. (1983)."},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.104.0278"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675757"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676174"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.3140"},{"key":"e_1_2_1_7_2","doi-asserted-by":"crossref","unstructured":"M. H.SchultzandE.Auth.Advanced automatic test pattern generation and redundancy identification techniques. FTCS\u201018 pp.30\u201335(June1988).","DOI":"10.1109\/FTCS.1988.5293"},{"key":"e_1_2_1_8_2","unstructured":"A.Motohara K.Nishimura H.FujiwaraandI.Shirakawa.A parallel scheme for test pattern generation. ICCAD\u201086 pp.156\u2013159(Nov.1986)."},{"key":"e_1_2_1_9_2","unstructured":"G. A.Kramer.Employing massive parallelism in digital ATPG algorithm. Proc. International Test Conference pp.108\u2013114(Oct.1983)."},{"issue":"5","key":"e_1_2_1_10_2","first-page":"522","article-title":"Dynamic two\u2010dimensional parallel method for high\u2010speed fault simulation by vector computer","volume":"29","author":"Ishiura N.","year":"1988","journal-title":"Trans. Inf. Proc. Soc., Japan"},{"key":"e_1_2_1_11_2","doi-asserted-by":"crossref","unstructured":"H.Wunderlich.Multiple distributions for biased random test patterns. Proc. International Test Conference pp.236\u2013244(Sept.1988).","DOI":"10.1109\/TEST.1988.207808"},{"key":"e_1_2_1_12_2","doi-asserted-by":"crossref","unstructured":"J. A.WaicukauskiandE.Lindbloom.Fault detection effectiveness of weighted random patterns. Proc. International Test Conference pp.245\u2013255(Sept.1988).","DOI":"10.1109\/TEST.1988.207809"},{"key":"e_1_2_1_13_2","unstructured":"M.Ito N.Ishiura andS.Yajima.Test generation by weighted random variable using high\u2010speed fault simulator. 38th Nat. Conv. Inf. Proc. Soc. Jap. 2S\u20104 (Spr.1989)."},{"key":"e_1_2_1_14_2","unstructured":"F.Hirose M.Ishii J.Niitsuma T.Shindo N.Kawato H.Hamamura K.Uchida andH.Yamada. Simulation Processor \u201cSP.\u201d ICCAD\u201087 pp.484\u2013487(Nov.1987)."},{"issue":"4","key":"e_1_2_1_15_2","first-page":"644","article-title":"Simulation processor SP","volume":"71","author":"Yamada H.","year":"1988","journal-title":"Trans. (D), I.E.I.C.E., Japan"},{"key":"e_1_2_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1975.218900"},{"key":"e_1_2_1_17_2","unstructured":"F.BrglezandH.Fujiwara.A neutral net list of 10 combinational benchmark circuits and a target translator in Fortran. Special Session on ATPG and Fault Simulation ISCAS 85 (1985)."},{"key":"e_1_2_1_18_2","unstructured":"H.Fujiwara. FAN: A fanout\u2010oriented test generation algorithm. ISCAS 85 pp.671\u2013674(1985)."},{"key":"e_1_2_1_19_2","unstructured":"B. C.ResalesandP.Goel.Results from application of a commercial ATG system to large\u2010scale combinational circuits. ISCAS 85 pp.667\u2013670(1985)."},{"key":"e_1_2_1_20_2","doi-asserted-by":"crossref","unstructured":"D. K.Beece G.Diebert G.Papp andF.Villante.The IBM engineering verification engine. Proc. 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