{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T18:40:28Z","timestamp":1737225628027,"version":"3.33.0"},"reference-count":18,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2007,3,22]],"date-time":"2007-03-22T00:00:00Z","timestamp":1174521600000},"content-version":"vor","delay-in-days":5924,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1991,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper proposes a hypercube network (HC) design on the wafer\u2010scale LSI (WSI). HC is considered interesting as a network structure, which is suited to the general or dedicated parallel processing machine. There also exist commercial HC machines. With the development of LSI fabrication technologies as the background, WSI is now feasible where a large\u2010scale parallel processing system is installed on a wafer.<\/jats:p><jats:p>The major problems in WSI are how to build in the required network structure on the planar structure wafer, and how to improve the yield by avoiding the defects generated in the fabrication process. In most of the past studies, the array (lattice) structure is employed in the realization of the network on WSI, and HC is seldom employed. In this paper sub\u2010HC with 2<jats:sup><jats:italic>P<\/jats:italic><\/jats:sup>PEs is constructed as the row network (RN); and by connecting 2<jats:sup><jats:italic>d\u2010p<\/jats:italic><\/jats:sup>RNs along the column direction, HC with 2<jats:sup><jats:italic>d<\/jats:italic><\/jats:sup>PEs is constructed.<\/jats:p><jats:p>In other words, RN is constructed by the Diogenes method to compose an HC as a one\u2010dimensional structure, and then the structure is extended to two dimensions by adding new switches and bus structures, resulting in a structure suited to WSI. Two structures are considered: the structure with redundant PE only in RN and the structure containing redundant RNs. A rough evaluation for the yield also is presented.<\/jats:p>","DOI":"10.1002\/scj.4690220404","type":"journal-article","created":{"date-parts":[[2007,7,7]],"date-time":"2007-07-07T20:53:14Z","timestamp":1183841594000},"page":"29-40","source":"Crossref","is-referenced-by-count":2,"title":["A hypercube design on wafer\u2010scale integration"],"prefix":"10.1002","volume":"22","author":[{"given":"Hideo","family":"Ito","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nobuyuki","family":"Suzuki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,22]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"crossref","DOI":"10.7551\/mitpress\/4792.001.0001","volume-title":"Multicomputer Networks","author":"Reed D. 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