{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T02:29:07Z","timestamp":1761964147534,"version":"3.33.0"},"reference-count":20,"publisher":"Wiley","issue":"6","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":4827,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>A number of methods for constructing fault\u2010tolerant parallel processors using one dimensional linear cellular automaton model have already been proposed. When the methods are used, however, a large amount of hardware is required to realize the connections among processing elements for executing a given algorithm, and for reconfiguring the processor quickly when faults occur in the processor. Moreover, these processors require long communication distances between processing elements so that the method is difficult to be used for large scale processors. In this paper, a method for constructing parallel processors based on a two dimensional cellular automaton model is proposed to alleviate the problems. In the processor based on this model, processing elements are connected in two dimension and the average communication distance can be reduced and a higher fault\u2010tolerance due to the increase in the number of communication paths from 2 to 4.<\/jats:p>","DOI":"10.1002\/scj.4690250601","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T02:50:15Z","timestamp":1183863015000},"page":"1-11","source":"Crossref","is-referenced-by-count":4,"title":["A fault\u2010tolerant parallel processor modeled by a two\u2010dimensional linear cellular automaton"],"prefix":"10.1002","volume":"25","author":[{"given":"Masataka","family":"Kawanaka","sequence":"first","affiliation":[]},{"given":"Masahiro","family":"Tsunoyama","sequence":"additional","affiliation":[]},{"given":"Sachio","family":"Naito","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"volume-title":"Introduction to Parallel Processing","author":"Watanabe K.","key":"e_1_2_1_2_2"},{"volume-title":"Parallel Processing Machine","year":"1989","author":"Tomita S.","key":"e_1_2_1_3_2"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675684"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"issue":"2","key":"e_1_2_1_6_2","first-page":"78","volume":"19","author":"Negrini R.","year":"1990","journal-title":"Fault\u2010tolerance techniques for array structures used in super computers. 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