{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T20:10:17Z","timestamp":1737231017654,"version":"3.33.0"},"reference-count":19,"publisher":"Wiley","issue":"9","license":[{"start":{"date-parts":[[2007,3,22]],"date-time":"2007-03-22T00:00:00Z","timestamp":1174521600000},"content-version":"vor","delay-in-days":4828,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper considers the processor with the parallel operation and lookahead control functions based on the real\u2010time system program. The relation between the logical dependencies among instructions and the performance improvement is analyzed. With respect to the dependency, the number of dynamic steps that are processed between logically dependent instructions is considered, and the histogram is examined in the program actually run.<\/jats:p><jats:p>A method is devised wherein the behavior of the processor executing the instructions following the written order is represented in terms of the probability based on the statistical data. The effects of the dependency and the number of functional units on the processor also is evaluated by a simulation. The validity of the proposed method is verified and the effect is evaluated of performance improvement when the order of instruction execution is made variable.<\/jats:p>","DOI":"10.1002\/scj.4690250901","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T03:22:33Z","timestamp":1183864953000},"page":"1-16","source":"Crossref","is-referenced-by-count":0,"title":["Estimating the performance of multiple functional unit and pipelined processor using statistical instruction dependencies"],"prefix":"10.1002","volume":"25","author":[{"given":"Yasuo","family":"Kinouchi","sequence":"first","affiliation":[]},{"given":"Takayuki","family":"Hoshiko","sequence":"additional","affiliation":[]},{"given":"Kouichi","family":"Inamori","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,22]]},"reference":[{"volume-title":"Computer Architecture and Parallel Processing","year":"1981","author":"Hwang K.","key":"e_1_2_1_2_2"},{"volume-title":"Parallel Processing","year":"1986","author":"Muraoka Y.","key":"e_1_2_1_3_2"},{"volume-title":"Construction of Parallel Computers","year":"1986","author":"Tomita S.","key":"e_1_2_1_4_2"},{"volume-title":"Computer Architecture: A Quantitative Approach","year":"1990","author":"Patterson D. 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