{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,29]],"date-time":"2023-09-29T08:15:51Z","timestamp":1695975351069},"reference-count":10,"publisher":"Wiley","issue":"9","license":[{"start":{"date-parts":[[2007,3,22]],"date-time":"2007-03-22T00:00:00Z","timestamp":1174521600000},"content-version":"vor","delay-in-days":4828,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1994,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>An efficient fault diagnostic method should be developed to reduce the turnaround time and the cost for developing binary LSI's. For the multiple\u2010valued logic system that has been expected in the post\u2010binary electronics, research on the fault diagnosis for the logic circuit will be essential.<\/jats:p><jats:p>This paper discusses the design and the fault diagnosis in multiple\u2010valued cellular arrays. First, the single\u2010level array, two\u2010level array, three\u2010level array, and <jats:italic>n<\/jats:italic>\u2010level array realizing <jats:italic>k<\/jats:italic>\u2010valued <jats:italic>n<\/jats:italic>\u2010variable logic functions are introduced. It is clarified that the two\u2010level array is the most suitable structure solving both problems of the number of cells and the fault location.<\/jats:p><jats:p>Next, further investigation is made for the fault diagnosis. The stuck\u2010at faults, the open fault, and the AND bridging fault are treated under the assumption that the single fault occurs in the array. In the authors' fault diagnostic method, the test inputs can easily be generated from the control inputs that specify the switches of cells. Moreover, the comparison with other testing methods for cellular arrays shows that our method reduces the order of steps for generating all test inputs.<\/jats:p>","DOI":"10.1002\/scj.4690250904","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T03:22:33Z","timestamp":1183864953000},"page":"41-52","source":"Crossref","is-referenced-by-count":2,"title":["Design and fault diagnosis of cellular arrays realizing multiple\u2010valued logic functions"],"prefix":"10.1002","volume":"25","author":[{"given":"Naotake","family":"Kamiura","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yutaka","family":"Hata","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazuharu","family":"Yamato","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,22]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009040"},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009170"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1970.222906"},{"issue":"9","key":"e_1_2_1_5_2","first-page":"734","article-title":"Minimum fault detection for NORNAND cellular arrays. Trans. I.E.I.C.E.","volume":"60","author":"Takamatsu Y.","year":"1977","journal-title":"Japan"},{"issue":"12","key":"e_1_2_1_6_2","first-page":"1191","volume":"26","author":"Bate J. A.","year":"1972","journal-title":"Three cell structures for ternary cellular arrays. IEEE Trans. Comput."},{"issue":"3","key":"e_1_2_1_7_2","first-page":"235","article-title":"Some realization of multivalued logic function with cellular arrays. I.E.I.C.E.","volume":"72","author":"Takanami I.","year":"1989","journal-title":"Trans."},{"issue":"9","key":"e_1_2_1_8_2","first-page":"693","article-title":"Fault test for cellular arrays realizing multivalued logic functions. Trans. I.E.I.C.E.","volume":"72","author":"Takanami I.","year":"1989","journal-title":"Japan"},{"issue":"3","key":"e_1_2_1_9_2","first-page":"412","article-title":"Design of a multiple\u2010valued cellular array. I.E.I.C.E.","volume":"76","author":"Kamiura N.","year":"1993","journal-title":"Trans. Electron."},{"key":"e_1_2_1_10_2","volume-title":"Fault diagnosis of digital circuits (part 1)","author":"Kinoshita K.","year":"1983"},{"key":"e_1_2_1_11_2","first-page":"1160","volume-title":"Multiple\u2010valued logic: Its status and its future","author":"Hurst S. L.","year":"1984"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690250904","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690250904","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,28]],"date-time":"2023-09-28T11:48:16Z","timestamp":1695901696000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690250904"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,1]]},"references-count":10,"journal-issue":{"issue":"9","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1002\/scj.4690250904"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690250904","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"value":"0882-1666","type":"print"},{"value":"1520-684X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1994,1]]}}}