{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T20:10:21Z","timestamp":1737231021081,"version":"3.33.0"},"reference-count":11,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":4462,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>The paper describes wafer\u2010scale memory design with network logic based on switching register circuit (SW\u2010REG), and defect tolerance schemes. Such a wafer\u2010scale memory is an array of chips, each consisting of a memory core and SW\u2010REG. The SW\u2010REG links neighboring chips of the same column, and each column is independently accessible from the outside. Monte Carlo simulation demonstrated that addition of driver transistors and spare lines to common signals, and bypass lines to SW\u2010REG are optimum defect tolerance schemes. When using 64 Mbit DRAM memory core on an 8\u2010inch wafer, wafer\u2010scale memory gives higher memory capacity than corresponding discrete chip system: for 5 percent memory core yield, 13 times higher memory capacity is achieved.<\/jats:p>","DOI":"10.1002\/scj.4690260201","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T06:16:44Z","timestamp":1183875404000},"page":"1-9","source":"Crossref","is-referenced-by-count":0,"title":["A study of network logic for wafer\u2010scale parallel\u2010access memory and a yield analysis"],"prefix":"10.1002","volume":"26","author":[{"given":"Koichi","family":"Yamashita","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shohei","family":"Ikehara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1986.13689"},{"key":"e_1_2_1_3_2","first-page":"141","article-title":"Potential and limitations of wafer\u2010scale LSI","volume":"422","author":"Yamashita K.","year":"1987","journal-title":"Nikkei Electronics"},{"key":"e_1_2_1_4_2","unstructured":"S.Horiguchi.Trends in WSI devices R&D Electronics Materials pp.16\u201324(May1991)."},{"key":"e_1_2_1_5_2","doi-asserted-by":"crossref","unstructured":"Y.Egawa N.TsudaandK.Masuda A 1M bit full wafer MOS RAM 1979 ISSCC pp.18\u201319(Feb.1979).","DOI":"10.1109\/ISSCC.1979.1156008"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051456"},{"key":"e_1_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052144"},{"key":"e_1_2_1_8_2","doi-asserted-by":"crossref","unstructured":"B.Warren W.Richardson K.Kanegawa H.Shimizu K.Nakai S.HaraandK.Ichiba.A One Megabit SRAM Fabricated with 1.2\u03bc Technology Proc. Int. Conf. Wafer Scale Integration pp.47\u2013153(Jan.1989).","DOI":"10.1109\/WAFER.1989.47535"},{"key":"e_1_2_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051050"},{"key":"e_1_2_1_10_2","doi-asserted-by":"crossref","unstructured":"N.MacDonald G.Neish A.Sinclair F.Baba T.Tatematsu K.HiraiwaandK.Miyasaka.200Mb Wafer Memory 1989 ISSCC pp.240\u2013241(Feb.1989).","DOI":"10.1109\/ISSCC.1989.48272"},{"key":"e_1_2_1_11_2","unstructured":"K.Yamashita S.Ikehara M.NagashimaandT.Tatematsu.A 600Mb Random\u2010Access Wafer\u2010Scale Memory Proc. IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems pp.322\u2013332(Nov.1990)."},{"key":"e_1_2_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12619"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690260201","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690260201","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T19:38:40Z","timestamp":1737229120000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690260201"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":11,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1002\/scj.4690260201"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690260201","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"type":"print","value":"0882-1666"},{"type":"electronic","value":"1520-684X"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}