{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T20:10:20Z","timestamp":1737231020565,"version":"3.33.0"},"reference-count":14,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":4462,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>This paper presents a new method for multiple fault diagnosis of combinational circuits using sensitizing input\u2010pairs. A partition of a circuit under test into subtree circuits and a generation method for diagnostic test are described. The set of diagnostic tests used in this paper is one of sensitizing input\u2010pairs that generate sensitizing paths including checkpoints on them.<\/jats:p><jats:p>By studying the relation between a sensitizing path generated by a sensitizing input\u2010pair and a subtree circuit, a method is presented for multiple fault diagnosis in the subtree circuit based on the fault\u2010free and the faulty responses observed at primary outputs. A deduction algorithm is described for a value at an output of a subtree circuit which does not have a primary output. The proposed method is applied to benchmark circuits having double faults, triple faults, and fourfold faults. Experimental results show that suspected faults are identified within 8 to 30 percent of all stuck\u2010at 0 and 1 faults on all lines in the circuit.<\/jats:p>","DOI":"10.1002\/scj.4690260302","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T08:16:54Z","timestamp":1183882614000},"page":"17-29","source":"Crossref","is-referenced-by-count":0,"title":["Multiple fault diagnosis in combinational circuits using sensitizing input\u2010pairs"],"prefix":"10.1002","volume":"26","author":[{"given":"Nobuhiro","family":"Yanagida","sequence":"first","affiliation":[]},{"given":"Hiroshi","family":"Takahashi","sequence":"additional","affiliation":[]},{"given":"Yuzo","family":"Takamatsu","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"volume-title":"Fault Diagnosis of Digital Systems","year":"1970","author":"Chang H. Y.","key":"e_1_2_1_2_2"},{"key":"e_1_2_1_3_2","doi-asserted-by":"crossref","unstructured":"P. G.Ryan S.RawatandW. K.Fuchs.Two\u2010stage fault location Proc. ITC pp.963\u2013968(Oct.\u2010Nov.1991).","DOI":"10.1109\/TEST.1991.519762"},{"key":"e_1_2_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675604"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1986.294966"},{"key":"e_1_2_1_6_2","doi-asserted-by":"crossref","unstructured":"M.Abramovici.A maximal resolution guided\u2010probe testing algorithm Proc. 18th DAC pp.189\u2013195(June1981).","DOI":"10.1109\/DAC.1981.1585351"},{"issue":"1","key":"e_1_2_1_7_2","first-page":"50","article-title":"Method for diagnosing multiple stuck\u2010at faults in combinational circuits","volume":"74","author":"Yamada Y.","year":"1991","journal-title":"I.E.I.C.E. Trans. Commun."},{"key":"e_1_2_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.3952"},{"key":"e_1_2_1_9_2","doi-asserted-by":"crossref","unstructured":"A.Verreault E. M.AboulhamidandY.Harkouri.Multiple fault analysis using a fault dropping technique Proc. FTCS\u201021 pp.162\u2013169(June1991).","DOI":"10.1109\/FTCS.1991.146656"},{"issue":"4","key":"e_1_2_1_10_2","first-page":"569","article-title":"A method of generating tests for combinational circuits with multiple faults","volume":"75","author":"Takahashi H.","year":"1992","journal-title":"I.E.I.C.E. Trans. Information and Systems"},{"key":"e_1_2_1_11_2","doi-asserted-by":"crossref","unstructured":"J.Kato T.ShimonoandM.Kawai.Fault diagnosis based on post\u2010test fault dictionary generation Proc. ITC pp.940(Aug.1989).","DOI":"10.1109\/TEST.1989.82392"},{"key":"e_1_2_1_12_2","unstructured":"J. A.Waicukauski V.GuptaandS.Patel.Diagnosis of BIST failures by PPSFP simulation Proc. ITC pp.480\u2013484(Sept.1987)."},{"key":"e_1_2_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/54.32421"},{"key":"e_1_2_1_14_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95424-5"},{"issue":"11","key":"e_1_2_1_15_2","first-page":"774","article-title":"A method for diagnosing single stuck\u2010at faults in combinational circuits","volume":"74","author":"Yamada T.","year":"1991","journal-title":"I.E.I.C.E. Trans. Commun."}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690260302","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690260302","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T19:39:19Z","timestamp":1737229159000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690260302"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":14,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1002\/scj.4690260302"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690260302","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"type":"print","value":"0882-1666"},{"type":"electronic","value":"1520-684X"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}