{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,27]],"date-time":"2023-10-27T15:12:11Z","timestamp":1698419531962},"reference-count":20,"publisher":"Wiley","issue":"7","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":4462,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[1995,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Because of its capability of high\u2010speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault\u2010tolerant techniques which are effective for on\u2010line use are proposed for TLB which is an example of the application of CAM.<\/jats:p><jats:p>First, fault and error models of the TLB consisting of the CAM part and the SRAM part are clarified. Then, the fault\u2010tolerant techniques for these faults and errors, such as distance separable technique, cod\u2010ing technique, simplified 1\u2010out\u2010of\u2010<jats:italic>n<\/jats:italic> check and graceful degradation, are proposed. The distance separable technique which encodes the data stored in the CAM part is the one which masks the faulty CAM part and prevents errors from propagating to the subsequent circuits. The coding technique checks the one\u2010to\u2010one correspondence between the data in the CAM and those in SRAM by using the SEC\u2010DED code with byte error detection capability, i.e., SEC\u2010DED\u2010SbED code, and at the same time it detects and corrects errors in the data stored in SRAM. The simplified 1\u2010out\u2010of\u2010<jats:italic>n<\/jats:italic> check processes association errors. The graceful degradation gives a flag in the faulty memory section and prevents it from being used.<\/jats:p><jats:p>The methods proposed in this paper are evaluated from area augmentation and error detection capability perspectives. The results show that the fault\u2010tolerant TLB with 32 virtual address bits, 32 physical address bits and 128 entries gives single fault detection probability of nearly 99 percent with 28 percent area increase.<\/jats:p>","DOI":"10.1002\/scj.4690260701","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T09:18:25Z","timestamp":1183886305000},"page":"1-12","source":"Crossref","is-referenced-by-count":1,"title":["Fault\u2010tolerant associate memories"],"prefix":"10.1002","volume":"26","author":[{"given":"Eiji","family":"Fujiwara","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsuyoshi","family":"Tanaka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"issue":"6","key":"e_1_2_1_2_2","first-page":"568","article-title":"Associative memories","volume":"27","author":"Ogura T.","year":"1986","journal-title":"Information Processing"},{"key":"e_1_2_1_3_2","doi-asserted-by":"crossref","unstructured":"M.Milenkovic.Microprocessor Memory Management Units. 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