{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T20:40:16Z","timestamp":1737232816432,"version":"3.33.0"},"reference-count":10,"publisher":"Wiley","issue":"11","license":[{"start":{"date-parts":[[2007,3,21]],"date-time":"2007-03-21T00:00:00Z","timestamp":1174435200000},"content-version":"vor","delay-in-days":4097,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp; Computers in Japan"],"published-print":{"date-parts":[[1996,1]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Wired\u2010logic is especially useful when designing fan\u2010in restricted logic circuits which are implemented with bipolar and MOS transistors. There is, however, little published on the subject outside of the work done by the present authors. In this paper, a method of reducing the levels of circuits by utilizing Wired\u2010Logic is presented. The method restricts the number of fanins for a gate utilizing Wired\u2010Logic and transforms circuits using the transduction method optimization. To attain the proper combination of NOR gates and Wired\u2010OR gates, an algorithm using Wired\u2010OR gates for the fan\u2010in restriction is also presented. By performing experiments on third level NOR circuits, the proposed method is comparable to<jats:italic>Generalized Serial Duplication<\/jats:italic>which is an efficient<jats:italic>serial duplication.<\/jats:italic>The levels of most circuits are reduced by Wired\u2010OR gates, thereby demonstrating the efficiency of Wired\u2010Logic. Although connection length is important to LSI, the cost function simplifies circuit levels. Hence, for the purposes of this paper, analysis is expanded to include the cost function.<\/jats:p>","DOI":"10.1002\/scj.4690271102","type":"journal-article","created":{"date-parts":[[2007,7,8]],"date-time":"2007-07-08T09:54:18Z","timestamp":1183888458000},"page":"19-28","source":"Crossref","is-referenced-by-count":0,"title":["Design of logic circuits with wired\u2010logic utilizing transduction method"],"prefix":"10.1002","volume":"27","author":[{"given":"Shigeru","family":"Yamashita","sequence":"first","affiliation":[]},{"given":"Yahiko","family":"Kambayashi","sequence":"additional","affiliation":[]},{"given":"Saburo","family":"Muroga","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2007,3,21]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1972.223426"},{"key":"e_1_2_1_3_2","unstructured":"Y.KambayashiandS.Muroga.Simplification of circuits based on permissible function (in Japanese). Technical Report of I.E.I.C.E. AL73\u201313 (1973)."},{"issue":"6","key":"e_1_2_1_4_2","doi-asserted-by":"crossref","first-page":"550","DOI":"10.1109\/TC.1986.5009432","article-title":"Properties of wired logic","volume":"35","author":"Kambayashi Y.","journal-title":"IEEE Trans. Comput."},{"key":"e_1_2_1_5_2","doi-asserted-by":"crossref","unstructured":"Y.MatsunagaandM.Fujita.Multi\u2010level logic optimization using binary decision diagrams. Proc. of International Conference of Computer Aided Design pp.556\u2013559(1989).","DOI":"10.1109\/ICCAD.1989.77012"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/12.35836"},{"key":"e_1_2_1_7_2","doi-asserted-by":"crossref","unstructured":"H.Sato Y.Yasue Y.MatsunagaandM.Fujita.Boolean resubstitution with permissible functions and binary decision diagrams. Proc. of 27th Design Automation Conference pp.284\u2013289(1989).","DOI":"10.1145\/123186.123276"},{"key":"e_1_2_1_8_2","unstructured":"Y.Kambayashi H. C.LaiandS.Muroga.Patternoriented transformations of NOR networks. UIUCDCS\u2010R\u201090\u20101573 Dept. Comput. Sci. Univ. of Illinois (1990)."},{"key":"e_1_2_1_9_2","unstructured":"T.Fujimoto H.HonjoandT.Kambe.Large network optimization using maximal CSPF. Report of Technical Group on Design Automation IPS Japan 91\u2010DA\u201060 pp.123\u2013130(1991)."},{"key":"e_1_2_1_10_2","unstructured":"S.Sawada Y.KambayashiandS.Muroga.Generation of fan\u2010in restricted initial networks for transduction method. Proc. the Synthesis and Simulation Meeting and International Interchange SASIMI'92 pp.36\u201345(1992)."},{"key":"e_1_2_1_11_2","unstructured":"H.Takada H.IshigakiandY.Kambayashi.A method for realization of fan\u2010in restricted transduction method based on efficient serial duplication (in Japanese). Proc. of the 46th Annual National Convention of IPS Japan 8M\u20104 (1993)."}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.4690271102","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.4690271102","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T20:14:44Z","timestamp":1737231284000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.4690271102"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1996,1]]},"references-count":10,"journal-issue":{"issue":"11","published-print":{"date-parts":[[1996,1]]}},"alternative-id":["10.1002\/scj.4690271102"],"URL":"https:\/\/doi.org\/10.1002\/scj.4690271102","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"type":"print","value":"0882-1666"},{"type":"electronic","value":"1520-684X"}],"subject":[],"published":{"date-parts":[[1996,1]]}}}