{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,12]],"date-time":"2025-01-12T00:10:16Z","timestamp":1736640616819,"version":"3.32.0"},"reference-count":18,"publisher":"Wiley","issue":"5","license":[{"start":{"date-parts":[[2006,10,30]],"date-time":"2006-10-30T00:00:00Z","timestamp":1162166400000},"content-version":"vor","delay-in-days":6756,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Softw Pract Exp"],"published-print":{"date-parts":[[1988,5]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>A front\u2010end of an electronic CAD synthesis system is described. The synthesis system accepts a behavioural description of a digital system design written in VHSIC Hardware Description Language (VHDL) and produces the physical hardware, at the register transfer level, needed for realizing the specified behaviour. The synthesis system comprises three major subsystems: process\u2010graph analyser, design representation and the MIMOLA synthesis system. The process\u2010graph analyser is an optimization and parallelization tool. We show how optimizing techniques used for compilers are adapted to perform a similar optimization function for hardware synthesis. We present techniques that extend the parallelization of the sequential programs concept for doing control state partitioning. The technique is new because of the unique synthesis model that MIMOLA uses. Finally, we show how to integrate these concepts using a suitable intermediate behavioural representation called the process graph.<\/jats:p>","DOI":"10.1002\/spe.4380180507","type":"journal-article","created":{"date-parts":[[2006,11,17]],"date-time":"2006-11-17T20:44:53Z","timestamp":1163796293000},"page":"469-483","source":"Crossref","is-referenced-by-count":3,"title":["Process\u2010graph analyser: A front\u2010end tool for VHDL behavioural synthesis"],"prefix":"10.1002","volume":"18","author":[{"given":"J.","family":"Bhasker","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2006,10,30]]},"reference":[{"key":"e_1_2_1_2_2","doi-asserted-by":"crossref","unstructured":"B. M.PangrleandD. D.Gajski \u2018State synthesis and connectivity binding for microarchitecture\u2019 Proc. ICCAD\u201386 1986 pp.210\u2013213.","DOI":"10.1097\/00000446-198602000-00043"},{"key":"e_1_2_1_3_2","doi-asserted-by":"crossref","unstructured":"A. C.Parker J.PizarroandM.Mlinar \u2018MAHA: a program for datapath synthesis\u2019 Proc. 23rd Design Automation Conf. 1986 pp.461\u2013466.","DOI":"10.1109\/DAC.1986.1586129"},{"key":"e_1_2_1_4_2","doi-asserted-by":"crossref","unstructured":"P. G.Paulin J. P.KnightandE. F.Girezye \u2018HAL: a multi\u2010paradigm approach to automatic data path synthesis\u2019 Proc. 23rd Design Automation Conf. 1986 pp.263\u2013270.","DOI":"10.1109\/DAC.1986.1586099"},{"key":"e_1_2_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270207"},{"key":"e_1_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270270"},{"issue":"3","key":"e_1_2_1_7_2","first-page":"337","article-title":"MDS \u2014 the Mimola design method","author":"Zimmerman G.","year":"1980","journal-title":"Journal of Digital Systems"},{"key":"e_1_2_1_8_2","unstructured":"VHDL Language Reference Manual Version 7.2 August 1985 Intermetrics."},{"key":"e_1_2_1_9_2","unstructured":"J. L.BaerandD. P.Bovet \u2018Compilation of arithmetic expressions for parallel computations\u2019 IFIP Congr. Proc. 1969 pp.340\u2013346."},{"key":"e_1_2_1_10_2","first-page":"119","volume-title":"Advances in Computers","author":"Kuck D. J.","year":"1976"},{"key":"e_1_2_1_11_2","unstructured":"Y.Muraoka \u2018Parallelism exposure and exploitation in programs\u2019 Ph.D. Dissertation Universtiy of Illinois at Urbana \u2010 Champaign 1971."},{"volume-title":"Principles of Compiler Design","year":"1979","author":"Aho A.","key":"e_1_2_1_12_2"},{"key":"e_1_2_1_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/360018.360025"},{"key":"e_1_2_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/359588.359596"},{"key":"e_1_2_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/321921.321939"},{"key":"e_1_2_1_16_2","doi-asserted-by":"publisher","DOI":"10.1137\/0204044"},{"key":"e_1_2_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/321921.321938"},{"key":"e_1_2_1_18_2","doi-asserted-by":"crossref","unstructured":"G. A.Kildall \u2018A unified approach to global program optimization\u2019 ACM Symp. Principles of Prog. Languages October1973 pp.194\u2013206.","DOI":"10.1145\/512927.512945"},{"volume-title":"Program Flow Analysis: Theory and Applications","year":"1981","author":"Muchnick S. S.","key":"e_1_2_1_19_2"}],"container-title":["Software: Practice and Experience"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fspe.4380180507","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/spe.4380180507","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T23:57:18Z","timestamp":1736639838000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/spe.4380180507"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1988,5]]},"references-count":18,"journal-issue":{"issue":"5","published-print":{"date-parts":[[1988,5]]}},"alternative-id":["10.1002\/spe.4380180507"],"URL":"https:\/\/doi.org\/10.1002\/spe.4380180507","archive":["Portico"],"relation":{},"ISSN":["0038-0644","1097-024X"],"issn-type":[{"type":"print","value":"0038-0644"},{"type":"electronic","value":"1097-024X"}],"subject":[],"published":{"date-parts":[[1988,5]]}}}