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However, challenges in controlling carrier mobility, carrier concentration, and defect density have hindered their deployment in advanced chip technologies. Here, we report a heterojunction oxide semiconductor channel approach that mitigates the interface\/channel defect density and achieves field\u2010effect mobility to &gt;100 cm\n                    <jats:sup>2<\/jats:sup>\n                    \/V.s, competitive with thin\u2010film silicon channels. By engineering a bilayer oxide channel, we demonstrate a low\u2010thermal\u2010budget, ultra\u2010scaled, memory\u2010logic dual\u2010mode ferroelectric transistor that exhibits a high on\u2010state current of 800\u00a0\u00b5A\/\u00b5m at V\n                    <jats:sub>d<\/jats:sub>\n                    \u00a0=\u00a01\u00a0V, a positive threshold voltage, and excellent reliability with only 30\u00a0mV threshold shift after 5000s of gate\u2010bias stress. Furthermore, it exhibits robust memory endurance exceeding 10\n                    <jats:sup>7<\/jats:sup>\n                    cycles and a fast ferroelectric read\u2010after\u2010write delay of 180\u00a0ns. TCAD simulation (Ginestra) reveals that performance improvement is attributed to the defect self\u2010compensation effect in bilayer channel, which stabilizes disordered metal bonds and weakly bonded oxygen states. This work establishes a pathway towards reliable, high\u2010performance oxide\u2010based transistors, offering a scalable solution for next\u2010generation low\u2010power reconfigurable chips tailored for generative artificial intelligence.\n                  <\/jats:p>","DOI":"10.1002\/adma.74279","type":"journal-article","created":{"date-parts":[[2026,7,31]],"date-time":"2026-07-31T14:33:12Z","timestamp":1785508392000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["High\u2010Mobility and Reliability Ultra\u2010Thin\u2010Channel Oxide Semiconductor Field\u2010Effect Transistors for Chip\u2010Interconnect\u2010Embedded Logic and Ferroelectric Memory"],"prefix":"10.1002","volume":"38","author":[{"given":"Chun\u2010Kuei","family":"Chen","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Singapore Hybrid\u2010Integrated Next\u2010Generation \u03bc\u2010Electronics Research Center (SHINE) National University of Singapore Singapore Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-3511-6408","authenticated-orcid":false,"given":"Sonu","family":"Hooda","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Singapore Hybrid\u2010Integrated Next\u2010Generation \u03bc\u2010Electronics Research Center (SHINE) National University of Singapore Singapore Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1344-292X","authenticated-orcid":false,"given":"Maheswari","family":"Sivan","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Singapore Hybrid\u2010Integrated Next\u2010Generation \u03bc\u2010Electronics Research Center (SHINE) National University of Singapore Singapore Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6111-2140","authenticated-orcid":false,"given":"Quanzhen","family":"Wan","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Singapore Hybrid\u2010Integrated Next\u2010Generation \u03bc\u2010Electronics Research Center (SHINE) National University of Singapore Singapore Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marco A.","family":"Villena","sequence":"additional","affiliation":[{"name":"Department of Electronics and Computer Technology University of Granada  Granada Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bastien","family":"Beltrando","sequence":"additional","affiliation":[{"name":"Applied Materials Inc.  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