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Here we report a mixed\u2010dimensional ternary CMOS (T\u2010CMOS) platform that monolithically integrates aligned carbon nanotubes (CNTs) and monolayer MoS\n                    <jats:sub>2<\/jats:sub>\n                    within silicon backend\u2010of\u2010line processes. The resulting CNT\u2010MoS\n                    <jats:sub>2<\/jats:sub>\n                    heterojunction transistors exhibit more than an order\u2010of\u2010magnitude performance improvement in output current and negative differential transconductance over previous ternary devices, enabling robust three\u2010level switching with large noise margins. By co\u2010fabricating CNT p\u2010FETs and MoS\n                    <jats:sub>2<\/jats:sub>\n                    n\u2010FETs into heterojunction devices, we realize CMOS\u2010compatible standard, positive and negative ternary inverters, as well as NMIN and NMAX logic gates. A fully functional ternary 2\u2010to\u20109 decoder, the most complex low\u2010dimensional ternary circuit to date, is also demonstrated. Dynamic measurements and calibrated simulations confirm the scalability, cascade capability, and robustness of the T\u2010CMOS architecture, providing a viable pathway toward large\u2010scale ternary integrated circuits beyond binary limits.\n                  <\/jats:p>","DOI":"10.1002\/adma.74880","type":"journal-article","created":{"date-parts":[[2026,9,2]],"date-time":"2026-09-02T07:07:01Z","timestamp":1788332821000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Mixed\u2010Dimensional 1D\/2D Ternary CMOS for High\u2010Performance Integrated Circuits"],"prefix":"10.1002","author":[{"given":"Meiqi","family":"Xi","sequence":"first","affiliation":[{"name":"Key Laboratory For the Physics and Chemistry of Nanodevices and Center for Carbon\u2010Based Electronics School of Electronics Peking University  Beijing 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