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Here, we present a monolithic three\u2010dimensional (3D) vertically stacked MVL architecture based on a tellurium (Te)\/indium\u2010gallium\u2010zinc\u2010oxide (IGZO) heterojunction field\u2010effect transistor (H\u2010FET) integrated with a crystallinity\u2010enhanced Te field\u2010effect transistor (CE\u2010Te FET). Engineered interfacial band alignment in the H\u2010FET induces carrier confinement and gate\u2010tunable electron\u2010dominated transport, enabling intrinsic ternary switching through controlled current modulation. Complementary channel engineering of the CE\u2010Te FET via oxidation and crystallinity recovery suppresses off\u2010state leakage and optimizes transconductance matching, stabilizing the intermediate logic state. Using low\u2010temperature CMOS\u2010compatible processes, we realize wafer\u2010scale vertically stacked ternary circuits exhibiting robust three\u2010level operation, high uniformity, and long\u2010term stability. System\u2010level analysis reveals substantial gains in logic density and area efficiency enabled by H\u2010FET\u2010assisted 3D integration. Furthermore, the ternary voltage characteristics are directly mapped to ternary weight neural networks, enabling high\u2010accuracy handwritten digit classification. This scalable inorganic 3D MVL platform establishes a practical pathway toward high\u2010density logic and multi\u2010valued neuromorphic computing architectures beyond conventional binary planar scaling.<\/jats:p>","DOI":"10.1002\/advs.77437","type":"journal-article","created":{"date-parts":[[2026,8,25]],"date-time":"2026-08-25T13:18:57Z","timestamp":1787663937000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Wafer\u2010Scale 3D Integration for High\u2010Density Multi\u2010Valued Neuromorphic Logic"],"prefix":"10.1002","author":[{"given":"Chang\u2010Hyeon","family":"Kim","sequence":"first","affiliation":[{"name":"School of Electrical and Electronics Engineering Chung\u2010Ang University  Seoul South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Min Seok","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electronics and Information Engineering Hansung University  Seoul South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Joong Bum","family":"Rhim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology  Cambridge Massachusetts USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6278-1613","authenticated-orcid":false,"given":"Tae In","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronic Engineering Program in Semiconductor Convergence Inha University  Incheon South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4332-051X","authenticated-orcid":false,"given":"Hyuck\u2010In","family":"Kwon","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering Chung\u2010Ang University  Seoul South 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