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While the access transistor occupies a substantial portion of the 1T\u20131M cell area, it does not contribute to information storage. Here, a 2M NOR Flash architecture is demonstrated in which two series\u2010connected charge\u2010trap transistors ( and ) simultaneously function as programmable memory elements and current\u2010controlling components, enabling conductance\u2010window extension and current\u2010path gating within a single device structure. Device measurements show that sequential programming of the two memory devices significantly extends the accessible current window, reducing the minimum read current from 72.7\u00a0nA to 4.22\u00a0pA while maintaining reliable inhibit behavior under array bias conditions. Hardware\u2010aware neural inference further demonstrates that the extended conductance window reduces inference power by approximately 45% across multiple neural networks. In addition, the second programmable memory device enables true\u2010off hardware pruning and  state modulation, allowing substantial reduction of inference power while maintaining classification accuracy. These dual functional roles establish a task\u2010adaptive operation framework, in which the proposed 2M NOR Flash architecture serves as a scalable device platform for energy\u2010efficient compute\u2010in\u2010memory\u00a0systems.<\/jats:p>","DOI":"10.1002\/advs.77797","type":"journal-article","created":{"date-parts":[[2026,9,27]],"date-time":"2026-09-27T18:00:31Z","timestamp":1790532031000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Dual\u2010Programmable 2M NOR Flash Architecture for Energy\u2010Efficient In\u2010Memory Computing"],"prefix":"10.1002","author":[{"given":"Suhan","family":"Kim","sequence":"first","affiliation":[{"name":"Department of Intelligent Semiconductor Engineering Chung\u2010Ang University Seoul Republic of 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