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Here, we present a magnetic\u2010tunnel\u2010junction\u2010based processing\u2010in\u2010memory architecture that unifies data storage and massively parallel probabilistic computation for stochastic and deterministic neural networks. By introducing bit\u2010paired stochastic and stable magnetic tunnel junctions, we realize a multi\u2010precision stochastic memory cell that transduces stored binary weights into variance\u2010tunable stochastic bitstreams in situ. We evaluate the architecture's versatility across three progressive regimes of stochastic neural computation. First, by using a hardware\u2010in\u2010the\u2010loop prototype interfacing fabricated stochastic spin\u2010orbit torque magnetic tunnel junctions with a field\u2010programmable gate array chip, we validate stochastic matrix\u2010vector multiplications and achieve near\u2010floating\u2010point accuracy without specialized retraining. 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This device\u2010circuit co\u2010design provides a shared hardware platform for stochastic neural inference, combinatorial optimization, and uncertainty\u2010aware computing.<\/jats:p>","DOI":"10.1002\/advs.78111","type":"journal-article","created":{"date-parts":[[2026,9,30]],"date-time":"2026-09-30T15:38:37Z","timestamp":1790782717000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Hardware Acceleration of Stochastic Neural Networks Enabled by Bit\u2010Cell Level Co\u2010Design of Magnetic Tunnel Junctions"],"prefix":"10.1002","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4764-3383","authenticated-orcid":false,"given":"Qiuyuan","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology  Cambridge Massachusetts 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