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With holistic codesign in both photonic and electronic domains, strategic electrical\u2010to\u2010optical signal conversion, a differential intensity\u2010modulation technique, and a dual rail\u2010to\u2010rail photodetection architecture, the monolithic photonic\u2010electronic test chip of a sign\u2010sign dot\u2010product accelerator achieves 8.92\u2010Gb\/s\/MAC computation throughput with 2.22\u2010pJ\/b\/MAC energy consumption for next\u2010generation large\u2010scale linear\u2010algebra computing hardware targeting higher than one TMAC\/s\/mm\n                    <jats:sup>2<\/jats:sup>\n                    computation density with only tens of fJ\/MAC energy consumption.\n                  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